mirror of https://github.com/llvm/circt.git
[RTL] Signed Math and comparisons (#279)
Add signed comparisons, arithmetic (signed) shift right, and signed math ops firrtl to rtl should use the fancy new signed ops match firrtl lowering semantics: had to check with the firrtl expert about the truncate in rem lowering for signed types
This commit is contained in:
Andrew Lenharth
GitHub
parent
1cdeeb783d
commit
86c0be773a
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@ -100,10 +100,13 @@ class UTVariadicRTLOp<string mnemonic, list<OpTrait> traits = []> :
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def AddOp : UTVariadicRTLOp<"add", [Commutative]>;
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def SubOp : UTBinRTLOp<"sub">;
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def MulOp : UTVariadicRTLOp<"mul", [Commutative]>;
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def DivOp : UTBinRTLOp<"div">;
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def ModOp : UTBinRTLOp<"mod">;
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def DivUOp : UTBinRTLOp<"divu">;
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def DivSOp : UTBinRTLOp<"divs">;
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def ModUOp : UTBinRTLOp<"modu">;
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def ModSOp : UTBinRTLOp<"mods">;
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def ShlOp : UTBinRTLOp<"shl">;
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def ShrOp : UTBinRTLOp<"shr">;
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def ShrUOp : UTBinRTLOp<"shru">;
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def ShrSOp : UTBinRTLOp<"shrs">;
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def AndOp : UTVariadicRTLOp<"and", [Commutative]>;
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def OrOp : UTVariadicRTLOp<"or", [Commutative]>;
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@ -23,7 +23,8 @@ public:
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return TypeSwitch<Operation *, ResultType>(op)
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.template Case<ConstantOp,
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// Arithmetic and Logical Binary Operations.
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AddOp, SubOp, MulOp, DivOp, ModOp, ShlOp, ShrOp,
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AddOp, SubOp, MulOp, DivUOp, DivSOp, ModUOp, ModSOp,
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ShlOp, ShrUOp, ShrSOp,
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// Bitwise operations
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AndOp, OrOp, XorOp,
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// Comparison operations
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@ -73,16 +74,19 @@ public:
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}
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// Basic nodes.
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HANDLE(ConstantOp, Unhandled)
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HANDLE(ConstantOp, Unhandled);
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// Arithmetic and Logical Binary Operations.
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HANDLE(AddOp, Binary);
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HANDLE(SubOp, Binary);
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HANDLE(MulOp, Binary);
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HANDLE(DivOp, Binary);
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HANDLE(ModOp, Binary);
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HANDLE(DivUOp, Binary);
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HANDLE(DivSOp, Binary);
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HANDLE(ModUOp, Binary);
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HANDLE(ModSOp, Binary);
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HANDLE(ShlOp, Binary);
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HANDLE(ShrOp, Binary);
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HANDLE(ShrUOp, Binary);
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HANDLE(ShrSOp, Binary);
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HANDLE(AndOp, Variadic);
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HANDLE(OrOp, Variadic);
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@ -536,7 +536,8 @@ struct FIRRTLLowering : public LowerFIRRTLToRTLBase<FIRRTLLowering>,
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// Binary Ops.
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template <typename ResultOpType>
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template <typename ResultUnsignedOpType,
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typename ResultSignedOpType = ResultUnsignedOpType>
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LogicalResult lowerBinOp(Operation *op);
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template <typename ResultOpType>
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LogicalResult lowerBinOpToVariadic(Operation *op);
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@ -580,7 +581,9 @@ struct FIRRTLLowering : public LowerFIRRTLToRTLBase<FIRRTLLowering>,
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LogicalResult visitExpr(MulPrimOp op) {
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return lowerBinOpToVariadic<rtl::MulOp>(op);
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}
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LogicalResult visitExpr(DivPrimOp op) { return lowerBinOp<rtl::DivOp>(op); }
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LogicalResult visitExpr(DivPrimOp op) {
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return lowerBinOp<rtl::DivUOp, rtl::DivSOp>(op);
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}
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LogicalResult visitExpr(RemPrimOp op);
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// Other Operations
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@ -956,7 +959,7 @@ LogicalResult FIRRTLLowering::lowerBinOpToVariadic(Operation *op) {
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/// lowerBinOp extends each operand to the destination type, then performs the
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/// specified binary operator.
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template <typename ResultOpType>
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template <typename ResultUnsignedOpType, typename ResultSignedOpType>
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LogicalResult FIRRTLLowering::lowerBinOp(Operation *op) {
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// Extend the two operands to match the destination type.
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auto resultType = op->getResult(0).getType();
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@ -966,7 +969,9 @@ LogicalResult FIRRTLLowering::lowerBinOp(Operation *op) {
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return failure();
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// Emit the result operation.
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return setLoweringTo<ResultOpType>(op, lhs, rhs);
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if (resultType.cast<IntType>().isSigned())
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return setLoweringTo<ResultSignedOpType>(op, lhs, rhs);
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return setLoweringTo<ResultUnsignedOpType>(op, lhs, rhs);
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}
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/// lowerCmpOp extends each operand to the longest type, then performs the
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@ -1003,10 +1008,17 @@ LogicalResult FIRRTLLowering::visitExpr(CatPrimOp op) {
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}
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LogicalResult FIRRTLLowering::visitExpr(RemPrimOp op) {
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// FIRRTL has the width of (a % b) = Min(W(a), W(b)) so we need to truncate
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// operands to the minimum width before doing the mod, not extend them.
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auto lhs = getLoweredValue(op.lhs());
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auto rhs = getLoweredValue(op.rhs());
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// FIRRTL has the width of (a % b) = Min(W(a), W(b)), but the operation is
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// done at max(W(a), W(b))) so we need to extend one operand, then truncate
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// the result.
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auto lhsFirTy = op.lhs().getType().dyn_cast<IntType>();
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auto rhsFirTy = op.rhs().getType().dyn_cast<IntType>();
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if (!lhsFirTy || !rhsFirTy || !lhsFirTy.hasWidth() || !rhsFirTy.hasWidth())
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return failure();
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auto opType = lhsFirTy.getWidth() > rhsFirTy.getWidth() ? lhsFirTy : rhsFirTy;
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auto lhs = getLoweredAndExtendedValue(op.lhs(), opType);
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auto rhs = getLoweredAndExtendedValue(op.rhs(), opType);
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if (!lhs || !rhs)
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return failure();
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@ -1016,13 +1028,13 @@ LogicalResult FIRRTLLowering::visitExpr(RemPrimOp op) {
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auto destWidth = unsigned(resultFirType.getWidthOrSentinel());
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auto resultType = builder->getIntegerType(destWidth);
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// Truncate either operand if required.
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if (lhs.getType().cast<IntegerType>().getWidth() != destWidth)
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lhs = builder->create<rtl::ExtractOp>(resultType, lhs, 0);
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if (rhs.getType().cast<IntegerType>().getWidth() != destWidth)
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rhs = builder->create<rtl::ExtractOp>(resultType, rhs, 0);
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return setLoweringTo<rtl::ModOp>(op, ValueRange({lhs, rhs}));
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Value modInst;
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if (resultFirType.isUnsigned()) {
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modInst = builder->create<rtl::ModUOp>(ValueRange({lhs, rhs}));
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} else {
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modInst = builder->create<rtl::ModSOp>(ValueRange({lhs, rhs}));
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}
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return setLoweringTo<rtl::ExtractOp>(op, resultType, modInst, 0);
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}
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//===----------------------------------------------------------------------===//
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@ -1109,7 +1121,7 @@ LogicalResult FIRRTLLowering::visitExpr(DShrPrimOp op) {
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// Zero extend or truncate the shift amount if needed.
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rhs = zeroExtendOrTruncate(rhs, lhs.getType(), *builder);
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return setLoweringTo<rtl::ShrOp>(op, lhs, rhs);
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return setLoweringTo<rtl::ShrUOp>(op, lhs, rhs);
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}
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LogicalResult FIRRTLLowering::visitExpr(TailPrimOp op) {
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@ -711,7 +711,8 @@ public:
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private:
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/// Emit the specified value as a subexpression to the stream.
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SubExprInfo emitSubExpr(Value exp, VerilogPrecedence parenthesizeIfLooserThan,
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bool forceExpectedSign = false);
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bool forceExpectedSign = false,
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bool opForceSign = false);
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SubExprInfo visitUnhandledExpr(Operation *op);
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SubExprInfo visitInvalidExpr(Operation *op) {
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@ -738,10 +739,15 @@ private:
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SubExprInfo emitBitSelect(Value operand, unsigned hiBit, unsigned loBit);
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SubExprInfo emitBinary(Operation *op, VerilogPrecedence prec,
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const char *syntax, bool hasStrictSign = false);
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const char *syntax, bool hasStrictSign = false,
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bool opForceSign = false);
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SubExprInfo emitVariadic(Operation *op, VerilogPrecedence prec,
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const char *syntax, bool hasStrictSign = false);
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const char *syntax, bool hasStrictSign = false,
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bool opForceSign = false);
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SubExprInfo emitRTLSignedVariadic(Operation *op, VerilogPrecedence prec,
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const char *syntax);
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/// Emit the specified subexpression in a context where the sign matters,
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/// e.g. for a less than comparison or divide.
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@ -749,6 +755,13 @@ private:
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const char *syntax) {
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return emitBinary(op, prec, syntax, /*hasStrictSign:*/ true);
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}
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/// Emit the specified subexpression in a context where the sign matters,
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/// e.g. for a less than comparison or divide.
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SubExprInfo emitRTLSignedBinary(Operation *op, VerilogPrecedence prec,
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const char *syntax) {
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return emitBinary(op, prec, syntax, /*hasStrictSign:*/ true,
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/*opForceSign*/ true);
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}
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SubExprInfo emitUnary(Operation *op, const char *syntax, bool forceUnsigned) {
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os << syntax;
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auto signedness = emitSubExpr(op->getOperand(0), Unary).signedness;
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@ -856,17 +869,22 @@ private:
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SubExprInfo visitComb(rtl::MulOp op) {
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return emitVariadic(op, Multiply, "*");
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}
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SubExprInfo visitComb(rtl::DivOp op) {
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return emitSignedBinary(op, Multiply, "/");
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SubExprInfo visitComb(rtl::DivUOp op) {
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return emitBinary(op, Multiply, "/");
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}
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SubExprInfo visitComb(rtl::ModOp op) {
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return emitSignedBinary(op, Multiply, "%");
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SubExprInfo visitComb(rtl::DivSOp op) {
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return emitRTLSignedBinary(op, Multiply, "/");
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}
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SubExprInfo visitComb(rtl::ShlOp op) {
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return emitSignedBinary(op, Shift, "<<");
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SubExprInfo visitComb(rtl::ModUOp op) {
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return emitBinary(op, Multiply, "%");
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}
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SubExprInfo visitComb(rtl::ShrOp op) {
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return emitSignedBinary(op, Shift, ">>>");
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SubExprInfo visitComb(rtl::ModSOp op) {
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return emitRTLSignedBinary(op, Multiply, "%");
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}
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SubExprInfo visitComb(rtl::ShlOp op) { return emitBinary(op, Shift, "<<"); }
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SubExprInfo visitComb(rtl::ShrUOp op) { return emitBinary(op, Shift, ">>>"); }
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SubExprInfo visitComb(rtl::ShrSOp op) {
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return emitRTLSignedBinary(op, Shift, ">>>");
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}
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SubExprInfo visitComb(rtl::AndOp op) { return emitVariadic(op, And, "&"); }
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SubExprInfo visitComb(rtl::OrOp op) { return emitVariadic(op, Or, "|"); }
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@ -883,10 +901,15 @@ private:
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// RTL Comparison Operations
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SubExprInfo visitComb(rtl::ICmpOp op) {
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std::array<const char *, 10> symop{"==", "!=", "<", "<=", "<",
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"<=", ">", ">=", ">", ">="};
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return emitSignedBinary(op, Comparison,
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symop[static_cast<uint64_t>(op.predicate())]);
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std::array<const char *, 10> symop{"==", "!=", "<", "<=", ">",
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">=", "<", "<=", ">", ">="};
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std::array<bool, 10> signop{false, false, true, true, true,
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true, false, false, false, false};
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auto pred = static_cast<uint64_t>(op.predicate());
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auto symopstr = symop[pred];
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if (signop[pred])
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return emitRTLSignedBinary(op, Comparison, symopstr);
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return emitBinary(op, Comparison, symopstr);
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}
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private:
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@ -918,8 +941,10 @@ std::string ExprEmitter::emitExpressionToString(Value exp,
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}
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SubExprInfo ExprEmitter::emitBinary(Operation *op, VerilogPrecedence prec,
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const char *syntax, bool hasStrictSign) {
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auto lhsInfo = emitSubExpr(op->getOperand(0), prec, hasStrictSign);
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const char *syntax, bool hasStrictSign,
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bool opForceSign) {
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auto lhsInfo =
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emitSubExpr(op->getOperand(0), prec, hasStrictSign, opForceSign);
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os << ' ' << syntax << ' ';
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// The precedence of the RHS operand must be tighter than this operator if
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@ -932,12 +957,15 @@ SubExprInfo ExprEmitter::emitBinary(Operation *op, VerilogPrecedence prec,
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if (rhsOperandOp && op->getName() == rhsOperandOp->getName())
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rhsPrec = prec;
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auto rhsInfo = emitSubExpr(op->getOperand(1), rhsPrec, hasStrictSign);
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auto rhsInfo =
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emitSubExpr(op->getOperand(1), rhsPrec, hasStrictSign, opForceSign);
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// If we have a strict sign, then match the firrtl operation sign.
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// Otherwise, the result is signed if both operands are signed.
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SubExprSignedness signedness;
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if (hasStrictSign)
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if (opForceSign)
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signedness = IsSigned;
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else if (hasStrictSign)
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signedness = getSignednessOf(op->getResult(0).getType());
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else if (lhsInfo.signedness == IsSigned && rhsInfo.signedness == IsSigned)
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signedness = IsSigned;
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@ -948,19 +976,26 @@ SubExprInfo ExprEmitter::emitBinary(Operation *op, VerilogPrecedence prec,
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}
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SubExprInfo ExprEmitter::emitVariadic(Operation *op, VerilogPrecedence prec,
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const char *syntax, bool hasStrictSign) {
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const char *syntax, bool hasStrictSign,
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bool opForceSign) {
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interleave(
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op->getOperands().begin(), op->getOperands().end(),
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[&](Value v1) { emitSubExpr(v1, prec, hasStrictSign); },
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[&](Value v1) { emitSubExpr(v1, prec, hasStrictSign, opForceSign); },
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[&] { os << ' ' << syntax << ' '; });
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return {prec, IsUnsigned};
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}
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SubExprInfo ExprEmitter::emitRTLSignedVariadic(Operation *op,
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VerilogPrecedence prec,
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const char *syntax) {
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return emitVariadic(op, prec, syntax, true, true);
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}
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/// Emit the specified value as a subexpression to the stream.
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SubExprInfo ExprEmitter::emitSubExpr(Value exp,
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VerilogPrecedence parenthesizeIfLooserThan,
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bool forceExpectedSign) {
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bool forceExpectedSign, bool opForceSign) {
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auto *op = exp.getDefiningOp();
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bool shouldEmitInlineExpr = op && isVerilogExpression(op);
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@ -972,7 +1007,8 @@ SubExprInfo ExprEmitter::emitSubExpr(Value exp,
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// If this is a non-expr or shouldn't be done inline, just refer to its
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// name.
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if (!shouldEmitInlineExpr) {
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if (forceExpectedSign && getSignednessOf(exp.getType()) != IsUnsigned) {
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if ((forceExpectedSign && getSignednessOf(exp.getType()) != IsUnsigned) ||
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opForceSign) {
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os << "$signed(" << emitter.getName(exp) << ')';
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return {Unary, IsSigned};
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}
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@ -12,7 +12,7 @@ firrtl.circuit "M1" {
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firrtl.connect %y, %c : !firrtl.flip<uint<8>>, !firrtl.uint<8>
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%d = rtl.mul %z, %z, %z : i8
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%e = rtl.mod %d, %c5 : i8
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%e = rtl.modu %d, %c5 : i8
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%f = rtl.concat %e, %z, %d : (i8, i8, i8) -> i8
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%g = firrtl.stdIntCast %f : (i8) -> !firrtl.uint<8>
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firrtl.connect %y, %g : !firrtl.flip<uint<8>>, !firrtl.uint<8>
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@ -7,87 +7,95 @@ module {
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// CHECK-LABEL: // external module E
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rtl.module @TESTSIMPLE(%a: i4, %cond: i1) -> (%r0: i4, %r1: i4, %r2: i4, %r3: i4, %r4: i4, %r5: i4, %r6: i4, %r7: i4, %r8: i4, %r9: i4,
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%r10: i1, %r11: i1, %r12: i1, %r13: i1, %r14: i1, %r15: i1, %r16: i1, %r17: i1, %r18: i1, %r19: i1,
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%r20: i1, %r21: i1, %r22: i1, %r23: i12, %r24: i2, %r25: i9, %r26: i9, %r27: i4
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) {
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%0 = rtl.add %a, %a : i4
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%1 = rtl.sub %a, %a : i4
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%2 = rtl.mul %a, %a : i4
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%3 = rtl.div %a, %a : i4
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%4 = rtl.mod %a, %a : i4
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%5 = rtl.shl %a, %a : i4
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%6 = rtl.shr %a, %a : i4
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%7 = rtl.or %a, %a : i4
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%8 = rtl.and %a, %a : i4
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%9 = rtl.xor %a, %a : i4
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%10 = rtl.icmp "eq" %a, %a : i4
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%11 = rtl.icmp "ne" %a, %a : i4
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%12 = rtl.icmp "slt" %a, %a : i4
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%13 = rtl.icmp "sle" %a, %a : i4
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%14 = rtl.icmp "sgt" %a, %a : i4
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%15 = rtl.icmp "sge" %a, %a : i4
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%16 = rtl.icmp "ult" %a, %a : i4
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%17 = rtl.icmp "ule" %a, %a : i4
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%18 = rtl.icmp "ugt" %a, %a : i4
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%19 = rtl.icmp "uge" %a, %a : i4
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%20 = rtl.andr %a : i4
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%21 = rtl.orr %a : i4
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%22 = rtl.xorr %a : i4
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%23 = rtl.concat %a, %a, %a : (i4, i4, i4) -> i12
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%24 = rtl.extract %a from 1 : (i4) -> i2
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%25 = rtl.sext %a : (i4) -> i9
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%26 = rtl.zext %a : (i4) -> i9
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%27 = rtl.mux %cond, %a, %a : i4
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rtl.module @TESTSIMPLE(%a: i4, %b: i4, %cond: i1) -> (
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%r0: i4, %r2: i4, %r4: i4, %r6: i4,
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%r7: i4, %r8: i4, %r9: i4, %r10: i4,
|
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%r11: i4, %r12: i4, %r13: i4, %r14: i4,
|
||||
%r15: i4, %r16: i1,
|
||||
%r17: i1, %r18: i1, %r19: i1, %r20: i1,
|
||||
%r21: i1, %r22: i1, %r23: i1, %r24: i1,
|
||||
%r25: i1, %r26: i1, %r27: i1, %r28: i1,
|
||||
%r29: i12, %r30: i2, %r31: i9, %r32: i9, %r33: i4
|
||||
) {
|
||||
|
||||
rtl.output %0, %1, %2, %3, %4, %5, %6, %7, %8, %9,
|
||||
%10, %11, %12, %13, %14, %15, %16, %17, %18, %19,
|
||||
%20, %21, %22, %23, %24, %25, %26, %27 :
|
||||
i4, i4, i4, i4, i4,
|
||||
i4, i4, i4, i4, i4,
|
||||
i1, i1, i1, i1, i1,
|
||||
i1, i1, i1, i1, i1,
|
||||
i1, i1, i1, i12, i2,
|
||||
i9, i9, i4
|
||||
%0 = rtl.add %a, %b : i4
|
||||
%2 = rtl.sub %a, %b : i4
|
||||
%4 = rtl.mul %a, %b : i4
|
||||
%6 = rtl.divu %a, %b : i4
|
||||
%7 = rtl.divs %a, %b : i4
|
||||
%8 = rtl.modu %a, %b : i4
|
||||
%9 = rtl.mods %a, %b : i4
|
||||
%10 = rtl.shl %a, %b : i4
|
||||
%11 = rtl.shru %a, %b : i4
|
||||
%12 = rtl.shrs %a, %b : i4
|
||||
%13 = rtl.or %a, %b : i4
|
||||
%14 = rtl.and %a, %b : i4
|
||||
%15 = rtl.xor %a, %b : i4
|
||||
%16 = rtl.icmp "eq" %a, %b : i4
|
||||
%17 = rtl.icmp "ne" %a, %b : i4
|
||||
%18 = rtl.icmp "slt" %a, %b : i4
|
||||
%19 = rtl.icmp "sle" %a, %b : i4
|
||||
%20 = rtl.icmp "sgt" %a, %b : i4
|
||||
%21 = rtl.icmp "sge" %a, %b : i4
|
||||
%22 = rtl.icmp "ult" %a, %b : i4
|
||||
%23 = rtl.icmp "ule" %a, %b : i4
|
||||
%24 = rtl.icmp "ugt" %a, %b : i4
|
||||
%25 = rtl.icmp "uge" %a, %b : i4
|
||||
%26 = rtl.andr %a : i4
|
||||
%27 = rtl.orr %a : i4
|
||||
%28 = rtl.xorr %a : i4
|
||||
%29 = rtl.concat %a, %a, %b : (i4, i4, i4) -> i12
|
||||
%30 = rtl.extract %a from 1 : (i4) -> i2
|
||||
%31 = rtl.sext %a : (i4) -> i9
|
||||
%32 = rtl.zext %a : (i4) -> i9
|
||||
%33 = rtl.mux %cond, %a, %b : i4
|
||||
|
||||
rtl.output %0, %2, %4, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15, %16, %17, %18, %19, %20, %21, %22, %23, %24, %25, %26, %27, %28, %29, %30, %31, %32, %33:
|
||||
i4,i4, i4,i4,i4,i4,i4, i4,i4,i4,i4,i4,
|
||||
i4,i1,i1,i1,i1, i1,i1,i1,i1,i1, i1,i1,i1,i1,
|
||||
i12, i2,i9,i9,i4
|
||||
}
|
||||
// CHECK-LABEL: module TESTSIMPLE(
|
||||
// CHECK-NEXT: input [3:0] a,
|
||||
// CHECK-NEXT: input [3:0] a, b
|
||||
// CHECK-NEXT: input cond,
|
||||
// CHECK-NEXT: output [3:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
|
||||
// CHECK-NEXT: output r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, r21, r22,
|
||||
// CHECK-NEXT: output [11:0] r23,
|
||||
// CHECK-NEXT: output [1:0] r24,
|
||||
// CHECK-NEXT: output [8:0] r25, r26,
|
||||
// CHECK-NEXT: output [3:0] r27);
|
||||
// CHECK-NEXT: output [3:0] r0, r2, r4, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15
|
||||
// CHECK-NEXT: output r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28
|
||||
// CHECK-NEXT: output [11:0] r29,
|
||||
// CHECK-NEXT: output [1:0] r30,
|
||||
// CHECK-NEXT: output [8:0] r31, r32,
|
||||
// CHECK-NEXT: output [3:0] r33);
|
||||
// CHECK-EMPTY:
|
||||
// CHECK-NEXT: assign r0 = a + a;
|
||||
// CHECK-NEXT: assign r1 = a - a;
|
||||
// CHECK-NEXT: assign r2 = a * a;
|
||||
// CHECK-NEXT: assign r3 = a / a;
|
||||
// CHECK-NEXT: assign r4 = a % a;
|
||||
// CHECK-NEXT: assign r5 = a << a;
|
||||
// CHECK-NEXT: assign r6 = a >>> a;
|
||||
// CHECK-NEXT: assign r7 = a | a;
|
||||
// CHECK-NEXT: assign r8 = a & a;
|
||||
// CHECK-NEXT: assign r9 = a ^ a;
|
||||
// CHECK-NEXT: assign r10 = a == a;
|
||||
// CHECK-NEXT: assign r11 = a != a;
|
||||
// CHECK-NEXT: assign r12 = a < a;
|
||||
// CHECK-NEXT: assign r13 = a <= a;
|
||||
// CHECK-NEXT: assign r14 = a < a;
|
||||
// CHECK-NEXT: assign r15 = a <= a;
|
||||
// CHECK-NEXT: assign r16 = a > a;
|
||||
// CHECK-NEXT: assign r17 = a >= a;
|
||||
// CHECK-NEXT: assign r18 = a > a;
|
||||
// CHECK-NEXT: assign r19 = a >= a;
|
||||
// CHECK-NEXT: assign r20 = &a;
|
||||
// CHECK-NEXT: assign r21 = |a;
|
||||
// CHECK-NEXT: assign r22 = ^a;
|
||||
// CHECK-NEXT: assign r23 = {a, a, a};
|
||||
// CHECK-NEXT: assign r24 = a[2:1];
|
||||
// CHECK-NEXT: assign r25 = {{[{}][{}]}}5{a[3]}}, a};
|
||||
// CHECK-NEXT: assign r26 = {{[{}][{}]}}5'd0}, a};
|
||||
// CHECK-NEXT: assign r27 = cond ? a : a;
|
||||
// CHECK-NEXT: assign r0 = a + b;
|
||||
// CHECK-NEXT: assign r2 = a - b;
|
||||
// CHECK-NEXT: assign r4 = a * b;
|
||||
// CHECK-NEXT: assign r6 = a / b;
|
||||
// CHECK-NEXT: assign r7 = $signed(a) / $signed(b);
|
||||
// CHECK-NEXT: assign r8 = a % b;
|
||||
// CHECK-NEXT: assign r9 = $signed(a) % $signed(b);
|
||||
// CHECK-NEXT: assign r10 = a << b;
|
||||
// CHECK-NEXT: assign r11 = a >>> b;
|
||||
// CHECK-NEXT: assign r12 = $signed(a) >>> $signed(b);
|
||||
// CHECK-NEXT: assign r13 = a | b;
|
||||
// CHECK-NEXT: assign r14 = a & b;
|
||||
// CHECK-NEXT: assign r15 = a ^ b;
|
||||
// CHECK-NEXT: assign r16 = a == b;
|
||||
// CHECK-NEXT: assign r17 = a != b;
|
||||
// CHECK-NEXT: assign r18 = $signed(a) < $signed(b);
|
||||
// CHECK-NEXT: assign r19 = $signed(a) <= $signed(b);
|
||||
// CHECK-NEXT: assign r20 = $signed(a) > $signed(b);
|
||||
// CHECK-NEXT: assign r21 = $signed(a) >= $signed(b);
|
||||
// CHECK-NEXT: assign r22 = a < b;
|
||||
// CHECK-NEXT: assign r23 = a <= b;
|
||||
// CHECK-NEXT: assign r24 = a > b;
|
||||
// CHECK-NEXT: assign r25 = a >= b;
|
||||
// CHECK-NEXT: assign r26 = &a;
|
||||
// CHECK-NEXT: assign r27 = |a;
|
||||
// CHECK-NEXT: assign r28 = ^a;
|
||||
// CHECK-NEXT: assign r29 = {a, a, b};
|
||||
// CHECK-NEXT: assign r30 = a[2:1];
|
||||
// CHECK-NEXT: assign r31 = {{[{}][{}]}}5{a[3]}}, a};
|
||||
// CHECK-NEXT: assign r32 = {{[{}][{}]}}5'd0}, a};
|
||||
// CHECK-NEXT: assign r33 = cond ? a : b;
|
||||
// CHECK-NEXT: endmodule
|
||||
|
||||
rtl.module @B(%a: i1 { rtl.inout }) -> (%b: i1, %c: i1) {
|
||||
|
|
|
|||
|
|
@ -103,20 +103,22 @@ module attributes {firrtl.mainModule = "Simple"} {
|
|||
|
||||
// CHECK-NEXT: [[ZEXTC1:%.+]] = rtl.zext [[CONCAT1]] : (i8) -> i12
|
||||
// CHECK-NEXT: [[ZEXT2:%.+]] = rtl.zext [[SUB]] : (i4) -> i12
|
||||
// CHECK-NEXT: [[VAL18:%.+]] = rtl.mul [[ZEXTC1]], [[ZEXT2]] : i12
|
||||
// CHECK-NEXT: [[VAL18:%.+]] = rtl.mul [[ZEXTC1]], [[ZEXT2]] : i12
|
||||
%18 = firrtl.mul %6, %2 : (!firrtl.uint<8>, !firrtl.uint<4>) -> !firrtl.uint<12>
|
||||
|
||||
// CHECK-NEXT: [[IN3SEXT:%.+]] = rtl.sext %in3 : (i8) -> i9
|
||||
// CHECK-NEXT: [[PADRESSEXT:%.+]] = rtl.sext [[PADRES]] : (i3) -> i9
|
||||
// CHECK-NEXT: = rtl.div [[IN3SEXT]], [[PADRESSEXT]] : i9
|
||||
// CHECK-NEXT: = rtl.divs [[IN3SEXT]], [[PADRESSEXT]] : i9
|
||||
%19 = firrtl.div %in3c, %3 : (!firrtl.sint<8>, !firrtl.sint<3>) -> !firrtl.sint<9>
|
||||
|
||||
// CHECK-NEXT: [[IN3TRUNC:%.+]] = rtl.extract %in3 from 0 : (i8) -> i3
|
||||
// CHECK-NEXT: = rtl.mod [[IN3TRUNC]], [[PADRES]] : i3
|
||||
// CHECK-NEXT: [[IN3EX:%.+]] = rtl.sext [[PADRES]] : (i3) -> i8
|
||||
// CHECK-NEXT: [[MOD1:%.+]] = rtl.mods %in3, [[IN3EX]] : i8
|
||||
// CHECK-NEXT: = rtl.extract [[MOD1]] from 0 : (i8) -> i3
|
||||
%20 = firrtl.rem %in3c, %3 : (!firrtl.sint<8>, !firrtl.sint<3>) -> !firrtl.sint<3>
|
||||
|
||||
// CHECK-NEXT: [[IN3TRUNC:%.+]] = rtl.extract %in3 from 0 : (i8) -> i3
|
||||
// CHECK-NEXT: = rtl.mod [[PADRES]], [[IN3TRUNC]] : i3
|
||||
// CHECK-NEXT: [[IN4EX:%.+]] = rtl.sext [[PADRES]] : (i3) -> i8
|
||||
// CHECK-NEXT: [[MOD2:%.+]] = rtl.mods [[IN4EX]], %in3 : i8
|
||||
// CHECK-NEXT: = rtl.extract [[MOD2]] from 0 : (i8) -> i3
|
||||
%21 = firrtl.rem %3, %in3c : (!firrtl.sint<3>, !firrtl.sint<8>) -> !firrtl.sint<3>
|
||||
|
||||
// CHECK-NEXT: [[WIRE:%n1]] = rtl.wire : i2
|
||||
|
|
@ -151,7 +153,7 @@ module attributes {firrtl.mainModule = "Simple"} {
|
|||
%28 = firrtl.andr %27 : (!firrtl.uint<12>) -> !firrtl.uint<1>
|
||||
|
||||
// CHECK-NEXT: = rtl.extract [[VAL18]] from 0 : (i12) -> i3
|
||||
// CHECK-NEXT: = rtl.shr [[XOR]], {{.*}} : i3
|
||||
// CHECK-NEXT: = rtl.shru [[XOR]], {{.*}} : i3
|
||||
%29 = firrtl.dshr %24, %18 : (!firrtl.uint<3>, !firrtl.uint<12>) -> !firrtl.uint<3>
|
||||
|
||||
// CHECK-NEXT: = rtl.zext %2 : (i3) -> i8
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@ func @shl_op(%a: i7, %b: i7) -> i7 {
|
|||
|
||||
// CHECK-LABEL: func @shr_op(%arg0: i7, %arg1: i7) -> i7 {
|
||||
func @shr_op(%a: i7, %b: i7) -> i7 {
|
||||
// CHECK-NEXT: [[RES:%[0-9]+]] = rtl.shr %arg0, %arg1 : i7
|
||||
%0 = rtl.shr %a, %b : i7
|
||||
// CHECK-NEXT: [[RES:%[0-9]+]] = rtl.shru %arg0, %arg1 : i7
|
||||
%0 = rtl.shru %a, %b : i7
|
||||
// CHECK-NEXT: return [[RES]]
|
||||
return %0 : i7
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue