mirror of https://github.com/llvm/circt.git
[Python] Update all create methods to accept keyword arguments. (#1167)
This makes the API more natural compared to an explicit dictionary of input ports to set by name.
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5ccb892b26
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7a2fa8d6da
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@ -26,7 +26,7 @@ class Test:
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def construct(self, mod):
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const = hw.ConstantOp.create(types.i32, 0)
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dummy = Dummy()
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inst = dummy.module.create("d", {"x": const.result})
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inst = dummy.module.create("d", x=const.result)
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try:
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# CHECK: cannot connect from source of type
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connect(inst.y, None)
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@ -20,135 +20,135 @@ with Context() as ctx, Location.unknown():
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const = hw.ConstantOp(i32, IntegerAttr.get(i32, 1))
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# CHECK: comb.extract %[[CONST]] from 14
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comb.ExtractOp.create(14, i32, {"input": const.result})
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comb.ExtractOp.create(14, i32, input=const.result)
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# CHECK: comb.extract %[[CONST]] from 14
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extract = comb.ExtractOp.create(14, i32)
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connect(extract.input, const.result)
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# CHECK: comb.parity %[[CONST]]
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comb.ParityOp.create(i32, {"input": const.result})
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comb.ParityOp.create(i32, input=const.result)
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# CHECK: comb.parity %[[CONST]]
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parity = comb.ParityOp.create(i32)
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connect(parity.input, const.result)
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# CHECK: comb.sext %[[CONST]]
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comb.SExtOp.create(i32, {"input": const.result})
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comb.SExtOp.create(i32, input=const.result)
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# CHECK: comb.sext %[[CONST]]
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sext = comb.SExtOp.create(i32)
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connect(sext.input, const.result)
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# CHECK: comb.divs %[[CONST]], %[[CONST]]
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comb.DivSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.DivSOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.divs %[[CONST]], %[[CONST]]
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divs = comb.DivSOp.create(i32)
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connect(divs.lhs, const.result)
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connect(divs.rhs, const.result)
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# CHECK: comb.divu %[[CONST]], %[[CONST]]
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comb.DivUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.DivUOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.divu %[[CONST]], %[[CONST]]
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divu = comb.DivUOp.create(i32)
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connect(divu.lhs, const.result)
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connect(divu.rhs, const.result)
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# CHECK: comb.mods %[[CONST]], %[[CONST]]
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comb.ModSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.ModSOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.mods %[[CONST]], %[[CONST]]
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mods = comb.ModSOp.create(i32)
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connect(mods.lhs, const.result)
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connect(mods.rhs, const.result)
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# CHECK: comb.modu %[[CONST]], %[[CONST]]
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comb.ModUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.ModUOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.modu %[[CONST]], %[[CONST]]
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modu = comb.ModUOp.create(i32)
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connect(modu.lhs, const.result)
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connect(modu.rhs, const.result)
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# CHECK: comb.shl %[[CONST]], %[[CONST]]
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comb.ShlOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.ShlOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.shl %[[CONST]], %[[CONST]]
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shl = comb.ShlOp.create(i32)
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connect(shl.lhs, const.result)
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connect(shl.rhs, const.result)
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# CHECK: comb.shrs %[[CONST]], %[[CONST]]
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comb.ShrSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.ShrSOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.shrs %[[CONST]], %[[CONST]]
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shrs = comb.ShrSOp.create(i32)
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connect(shrs.lhs, const.result)
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connect(shrs.rhs, const.result)
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# CHECK: comb.shru %[[CONST]], %[[CONST]]
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comb.ShrUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.ShrUOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.shru %[[CONST]], %[[CONST]]
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shru = comb.ShrUOp.create(i32)
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connect(shru.lhs, const.result)
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connect(shru.rhs, const.result)
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# CHECK: comb.sub %[[CONST]], %[[CONST]]
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comb.SubOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.SubOp.create(i32, lhs=const.result, rhs=const.result)
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# CHECK: comb.sub %[[CONST]], %[[CONST]]
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sub = comb.SubOp.create(i32)
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connect(sub.lhs, const.result)
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connect(sub.rhs, const.result)
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# CHECK: comb.icmp eq %[[CONST]], %[[CONST]]
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comb.EqOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.EqOp.create(i32, lhs=const.result, rhs=const.result)
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eq = comb.EqOp.create(i32)
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connect(eq.lhs, const.result)
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connect(eq.rhs, const.result)
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# CHECK: comb.icmp ne %[[CONST]], %[[CONST]]
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comb.NeOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.NeOp.create(i32, lhs=const.result, rhs=const.result)
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ne = comb.NeOp.create(i32)
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connect(ne.lhs, const.result)
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connect(ne.rhs, const.result)
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# CHECK: comb.icmp slt %[[CONST]], %[[CONST]]
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comb.LtSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.LtSOp.create(i32, lhs=const.result, rhs=const.result)
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lts = comb.LtSOp.create(i32)
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connect(lts.lhs, const.result)
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connect(lts.rhs, const.result)
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# CHECK: comb.icmp sle %[[CONST]], %[[CONST]]
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comb.LeSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.LeSOp.create(i32, lhs=const.result, rhs=const.result)
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les = comb.LeSOp.create(i32)
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connect(les.lhs, const.result)
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connect(les.rhs, const.result)
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# CHECK: comb.icmp sgt %[[CONST]], %[[CONST]]
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comb.GtSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.GtSOp.create(i32, lhs=const.result, rhs=const.result)
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gts = comb.GtSOp.create(i32)
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connect(gts.lhs, const.result)
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connect(gts.rhs, const.result)
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# CHECK: comb.icmp sge %[[CONST]], %[[CONST]]
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comb.GeSOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.GeSOp.create(i32, lhs=const.result, rhs=const.result)
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ges = comb.GeSOp.create(i32)
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connect(ges.lhs, const.result)
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connect(ges.rhs, const.result)
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# CHECK: comb.icmp ult %[[CONST]], %[[CONST]]
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comb.LtUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.LtUOp.create(i32, lhs=const.result, rhs=const.result)
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ltu = comb.LtUOp.create(i32)
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connect(ltu.lhs, const.result)
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connect(ltu.rhs, const.result)
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# CHECK: comb.icmp ule %[[CONST]], %[[CONST]]
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comb.LeUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.LeUOp.create(i32, lhs=const.result, rhs=const.result)
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leu = comb.LeUOp.create(i32)
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connect(leu.lhs, const.result)
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connect(leu.rhs, const.result)
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# CHECK: comb.icmp ugt %[[CONST]], %[[CONST]]
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comb.GtUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.GtUOp.create(i32, lhs=const.result, rhs=const.result)
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gtu = comb.GtUOp.create(i32)
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connect(gtu.lhs, const.result)
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connect(gtu.rhs, const.result)
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# CHECK: comb.icmp uge %[[CONST]], %[[CONST]]
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comb.GeUOp.create(i32, {"lhs": const.result, "rhs": const.result})
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comb.GeUOp.create(i32, lhs=const.result, rhs=const.result)
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geu = comb.GeUOp.create(i32)
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connect(geu.lhs, const.result)
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connect(geu.rhs, const.result)
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@ -27,7 +27,7 @@ with Context() as ctx, Location.unknown():
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body_builder=lambda module: hw.OutputOp([]))
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with InsertionPoint.at_block_terminator(top.body.blocks[0]):
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inst = op.create("inst1", {})
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inst = op.create("inst1")
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msft.locate(inst.operation, "mem", devtype=msft.M20K, x=50, y=100, num=1)
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# CHECK: hw.instance "inst1" @MyWidget() {"loc:mem" = #msft.physloc<M20K, 50, 100, 1>, parameters = {}} : () -> ()
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@ -95,10 +95,10 @@ with Context() as ctx, Location.unknown():
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inst1 = one_output.create("inst1")
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# CHECK: hw.instance "inst2" @one_input(%[[INST1_RESULT]])
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inst2 = one_input.create("inst2", {"a": inst1.a})
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inst2 = one_input.create("inst2", a=inst1.a)
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# CHECK: hw.instance "inst4" @two_inputs(%[[INST1_RESULT]], %[[INST1_RESULT]])
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inst4 = two_inputs.create("inst4", {"a": inst1.a})
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inst4 = two_inputs.create("inst4", a=inst1.a)
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connect(inst4.b, inst1.a)
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# CHECK: %[[INST5_RESULT:.+]] = hw.instance "inst5" @MyWidget(%[[INST5_RESULT]])
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@ -106,7 +106,7 @@ with Context() as ctx, Location.unknown():
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connect(inst5.my_input, inst5.my_output)
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# CHECK: hw.instance "inst6" {{.*}} {BANKS = 2 : i64}
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one_input.create("inst6", {"a": inst1.a}, parameters={"BANKS": 2})
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one_input.create("inst6", a=inst1.a, parameters={"BANKS": 2})
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instance_builder_tests = hw.HWModuleOp(name="instance_builder_tests",
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body_builder=instance_builder_body)
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@ -40,7 +40,7 @@ with Context() as ctx, Location.unknown():
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# CHECK: unknown port name b
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try:
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inst2 = one_input.create("inst2", {"a": constant_value})
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inst2 = one_input.create("inst2", a=constant_value)
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connect(inst2.b, constant_value)
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except AttributeError as e:
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print(e)
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@ -48,7 +48,7 @@ with Context() as ctx, Location.unknown():
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seq.reg(reg_input, module.clk, name="FuBar")
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# CHECK: seq.compreg %[[INPUT_VAL]], %clk {name = "reg1"}
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reg1 = seq.CompRegOp.create(i32, {"clk": module.clk}, name="reg1")
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reg1 = seq.CompRegOp.create(i32, clk=module.clk, name="reg1")
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connect(reg1.input, reg_input)
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# CHECK: seq.compreg %[[INPUT_VAL]], %clk {name = "reg2"}
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@ -19,8 +19,8 @@ def UnaryOp(base):
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class _Class(base):
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@classmethod
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def create(cls, *args, **kwargs):
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return UnaryOpBuilder(cls, *args, **kwargs)
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def create(cls, result_type, **kwargs):
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return UnaryOpBuilder(cls, result_type, kwargs)
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return _Class
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@ -47,8 +47,8 @@ def BinaryOp(base):
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class _Class(base):
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@classmethod
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def create(cls, *args, **kwargs):
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return BinaryOpBuilder(cls, *args, **kwargs)
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def create(cls, result_type, **kwargs):
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return BinaryOpBuilder(cls, result_type, kwargs)
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return _Class
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@ -57,8 +57,8 @@ def BinaryOp(base):
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class ExtractOp:
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@staticmethod
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def create(low_bit, *args, **kwargs):
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return ExtractOpBuilder(low_bit, *args, **kwargs)
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def create(low_bit, result_type, **kwargs):
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return ExtractOpBuilder(low_bit, result_type, kwargs)
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@UnaryOp
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@ -139,13 +139,13 @@ class ModuleLike:
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def create(self,
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name: str,
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input_port_mapping: Dict[str, Value] = {},
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parameters: Dict[str, object] = {},
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loc=None,
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ip=None):
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ip=None,
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**kwargs):
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return InstanceBuilder(self,
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name,
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input_port_mapping,
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kwargs,
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parameters=parameters,
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loc=loc,
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ip=ip)
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@ -56,5 +56,15 @@ class CompRegOp:
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)
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@classmethod
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def create(cls, *args, **kwargs):
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return CompRegBuilder(cls, *args, **kwargs)
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def create(cls,
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result_type,
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reset=None,
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reset_value=None,
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name=None,
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**kwargs):
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return CompRegBuilder(cls,
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result_type,
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kwargs,
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reset=reset,
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reset_value=reset_value,
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name=name)
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@ -32,8 +32,8 @@ def CompareOp(predicate):
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class _Class(cls):
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@staticmethod
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def create(*args, **kwargs):
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return ICmpOpBuilder(predicate, *args, **kwargs)
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def create(result_type, **kwargs):
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return ICmpOpBuilder(predicate, result_type, kwargs)
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return _Class
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@ -5,6 +5,8 @@
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# Generated tablegen dialects end up in the mlir.dialects package for now.
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from mlir.dialects._seq_ops_gen import *
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from .seq import CompRegOp
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# Create a computational register whose input is the given value, and is clocked
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# by the given clock. If a reset is provided, the register will be reset by that
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@ -19,11 +21,12 @@ def reg(value, clock, reset=None, reset_value=None, name=None):
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if not reset_value:
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zero = IntegerAttr.get(value_type, 0)
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reset_value = hw.ConstantOp(value_type, zero).result
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return CompRegOp(value_type,
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value,
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clock,
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reset=reset,
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reset_value=reset_value,
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name=name).result
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return CompRegOp.create(value_type,
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input=value,
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clk=clock,
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reset=reset,
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reset_value=reset_value,
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name=name).data.value
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else:
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return CompRegOp(value_type, value, clock, name=name).result
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return CompRegOp.create(value_type, input=value, clk=clock,
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name=name).data.value
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