mirror of https://github.com/llvm/circt.git
[NFC] Rename confusing api.
.get() on a type should construct a new type. BaseAlias was using this function to ALSO return the wrapped type. Rename the accessor to not conflict with the factory.
This commit is contained in:
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6ef649eb43
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76cda20533
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@ -233,7 +233,7 @@ def FEnumCreateOp : FIRRTLOp<"enumcreate"> {
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let extraClassDeclaration = [{
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/// Return the name attribute of the accessed field.
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StringAttr getFieldNameAttr() {
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return getResult().getType().get().getElementNameAttr(getFieldIndex());
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return getResult().getType().base().getElementNameAttr(getFieldIndex());
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}
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/// Return the name of the accessed field.
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@ -337,7 +337,7 @@ def SubindexOp : FIRRTLExprOp<"subindex"> {
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let firrtlExtraClassDeclaration = [{
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/// Return a `FieldRef` to the accessed field.
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FieldRef getAccessedField() {
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return FieldRef(getInput(), getInput().getType().get().getFieldID(getIndex()));
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return FieldRef(getInput(), getInput().getType().base().getFieldID(getIndex()));
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}
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using InputType = FVectorType;
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}];
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@ -464,13 +464,13 @@ def SubtagOp : FIRRTLExprOp<"subtag"> {
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let firrtlExtraClassDeclaration = [{
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/// Return a `FieldRef` to the accessed field.
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FieldRef getAccessedField() {
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return FieldRef(getInput(), getInput().getType().get()
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return FieldRef(getInput(), getInput().getType().base()
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.getFieldID(getFieldIndex()));
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}
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/// Return the name of the accessed field.
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StringAttr getFieldNameAttr() {
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return getInput().getType().get().getElementNameAttr(getFieldIndex());
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return getInput().getType().base().getElementNameAttr(getFieldIndex());
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}
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/// Return the name of the accessed field.
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@ -612,7 +612,7 @@ public:
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// Support C++ implicit conversions to BaseTy.
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operator BaseTy() const { return circt::firrtl::type_cast<BaseTy>(*this); }
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BaseTy get() const { return circt::firrtl::type_cast<BaseTy>(*this); }
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BaseTy base() const { return circt::firrtl::type_cast<BaseTy>(*this); }
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};
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} // namespace firrtl
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@ -1210,7 +1210,7 @@ static SmallVector<SubfieldOp> getAllFieldAccesses(Value structValue,
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assert(isa<SubfieldOp>(op));
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auto fieldAccess = cast<SubfieldOp>(op);
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auto elemIndex =
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fieldAccess.getInput().getType().get().getElementIndex(field);
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fieldAccess.getInput().getType().base().getElementIndex(field);
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if (elemIndex && *elemIndex == fieldAccess.getFieldIndex())
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accesses.push_back(fieldAccess);
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}
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@ -443,7 +443,7 @@ OpFoldResult DivPrimOp::fold(FoldAdaptor adaptor) {
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/// supersede any division with invalid or zero. Division of invalid by
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/// invalid should be one.
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if (getLhs() == getRhs()) {
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auto width = getType().get().getWidthOrSentinel();
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auto width = getType().base().getWidthOrSentinel();
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if (width == -1)
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width = 2;
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// Only fold if we have at least 1 bit of width to represent the `1` value.
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@ -522,7 +522,7 @@ OpFoldResult DShrPrimOp::fold(FoldAdaptor adaptor) {
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return constFoldFIRRTLBinaryOp(
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*this, adaptor.getOperands(), BinOpKind::DivideOrShift,
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[=](const APSInt &a, const APSInt &b) -> APInt {
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return getType().get().isUnsigned() || !a.getBitWidth() ? a.lshr(b)
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return getType().base().isUnsigned() || !a.getBitWidth() ? a.lshr(b)
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: a.ashr(b);
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});
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}
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@ -623,7 +623,8 @@ OpFoldResult XorPrimOp::fold(FoldAdaptor adaptor) {
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/// xor(x, x) -> 0
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if (getLhs() == getRhs())
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return getIntAttr(
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getType(), APInt(std::max(getType().get().getWidthOrSentinel(), 0), 0));
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getType(),
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APInt(std::max(getType().base().getWidthOrSentinel(), 0), 0));
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return constFoldFIRRTLBinaryOp(
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*this, adaptor.getOperands(), BinOpKind::Normal,
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@ -643,14 +644,14 @@ void LEQPrimOp::getCanonicalizationPatterns(RewritePatternSet &results,
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}
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OpFoldResult LEQPrimOp::fold(FoldAdaptor adaptor) {
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bool isUnsigned = getLhs().getType().get().isUnsigned();
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bool isUnsigned = getLhs().getType().base().isUnsigned();
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// leq(x, x) -> 1
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if (getLhs() == getRhs())
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return getIntAttr(getType(), APInt(1, 1));
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// Comparison against constant outside type bounds.
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if (auto width = getLhs().getType().get().getWidth()) {
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if (auto width = getLhs().getType().base().getWidth()) {
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if (auto rhsCst = getConstant(adaptor.getRhs())) {
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auto commonWidth = std::max<int32_t>(*width, rhsCst->getBitWidth());
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commonWidth = std::max(commonWidth, 1);
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@ -961,7 +962,7 @@ OpFoldResult AsSIntPrimOp::fold(FoldAdaptor adaptor) {
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// Be careful to only fold the cast into the constant if the size is known.
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// Otherwise width inference may produce differently-sized constants if the
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// sign changes.
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if (getType().get().hasWidth())
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if (getType().base().hasWidth())
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if (auto cst = getConstant(adaptor.getInput()))
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return getIntAttr(getType(), *cst);
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@ -981,7 +982,7 @@ OpFoldResult AsUIntPrimOp::fold(FoldAdaptor adaptor) {
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// Be careful to only fold the cast into the constant if the size is known.
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// Otherwise width inference may produce differently-sized constants if the
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// sign changes.
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if (getType().get().hasWidth())
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if (getType().base().hasWidth())
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if (auto cst = getConstant(adaptor.getInput()))
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return getIntAttr(getType(), *cst);
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@ -1023,7 +1024,7 @@ OpFoldResult CvtPrimOp::fold(FoldAdaptor adaptor) {
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// Signed to signed is a noop, unsigned operands prepend a zero bit.
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if (auto cst = getExtendedConstant(getOperand(), adaptor.getInput(),
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getType().get().getWidthOrSentinel()))
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getType().base().getWidthOrSentinel()))
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return getIntAttr(getType(), *cst);
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return {};
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@ -1041,7 +1042,7 @@ OpFoldResult NegPrimOp::fold(FoldAdaptor adaptor) {
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// FIRRTL negate always adds a bit.
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// -x ---> 0-sext(x) or 0-zext(x)
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if (auto cst = getExtendedConstant(getOperand(), adaptor.getInput(),
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getType().get().getWidthOrSentinel()))
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getType().base().getWidthOrSentinel()))
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return getIntAttr(getType(), APInt((*cst).getBitWidth(), 0) - *cst);
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return {};
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@ -1052,7 +1053,7 @@ OpFoldResult NotPrimOp::fold(FoldAdaptor adaptor) {
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return {};
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if (auto cst = getExtendedConstant(getOperand(), adaptor.getInput(),
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getType().get().getWidthOrSentinel()))
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getType().base().getWidthOrSentinel()))
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return getIntAttr(getType(), ~*cst);
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return {};
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@ -1471,14 +1472,14 @@ OpFoldResult PadPrimOp::fold(FoldAdaptor adaptor) {
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return input;
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// Need to know the input width.
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auto inputType = input.getType().get();
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auto inputType = input.getType().base();
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int32_t width = inputType.getWidthOrSentinel();
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if (width == -1)
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return {};
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// Constant fold.
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if (auto cst = getConstant(adaptor.getInput())) {
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auto destWidth = getType().get().getWidthOrSentinel();
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auto destWidth = getType().base().getWidthOrSentinel();
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if (destWidth == -1)
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return {};
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@ -1545,7 +1546,7 @@ OpFoldResult ShrPrimOp::fold(FoldAdaptor adaptor) {
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}
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LogicalResult ShrPrimOp::canonicalize(ShrPrimOp op, PatternRewriter &rewriter) {
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auto inputWidth = op.getInput().getType().get().getWidthOrSentinel();
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auto inputWidth = op.getInput().getType().base().getWidthOrSentinel();
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if (inputWidth <= 0)
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return failure();
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@ -1553,7 +1554,7 @@ LogicalResult ShrPrimOp::canonicalize(ShrPrimOp op, PatternRewriter &rewriter) {
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unsigned shiftAmount = op.getAmount();
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if (int(shiftAmount) >= inputWidth) {
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// shift(x, 32) => 0 when x has 32 bits. This is handled by fold().
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if (op.getType().get().isUnsigned())
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if (op.getType().base().isUnsigned())
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return failure();
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// Shifting a signed value by the full width is actually taking the
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@ -1568,7 +1569,7 @@ LogicalResult ShrPrimOp::canonicalize(ShrPrimOp op, PatternRewriter &rewriter) {
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LogicalResult HeadPrimOp::canonicalize(HeadPrimOp op,
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PatternRewriter &rewriter) {
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auto inputWidth = op.getInput().getType().get().getWidthOrSentinel();
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auto inputWidth = op.getInput().getType().base().getWidthOrSentinel();
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if (inputWidth <= 0)
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return failure();
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@ -1584,7 +1585,7 @@ OpFoldResult HeadPrimOp::fold(FoldAdaptor adaptor) {
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if (hasKnownWidthIntTypes(*this))
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if (auto cst = getConstant(adaptor.getInput())) {
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int shiftAmount =
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getInput().getType().get().getWidthOrSentinel() - getAmount();
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getInput().getType().base().getWidthOrSentinel() - getAmount();
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return getIntAttr(getType(), cst->lshr(shiftAmount).trunc(getAmount()));
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}
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@ -1595,13 +1596,13 @@ OpFoldResult TailPrimOp::fold(FoldAdaptor adaptor) {
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if (hasKnownWidthIntTypes(*this))
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if (auto cst = getConstant(adaptor.getInput()))
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return getIntAttr(getType(),
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cst->trunc(getType().get().getWidthOrSentinel()));
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cst->trunc(getType().base().getWidthOrSentinel()));
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return {};
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}
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LogicalResult TailPrimOp::canonicalize(TailPrimOp op,
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PatternRewriter &rewriter) {
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auto inputWidth = op.getInput().getType().get().getWidthOrSentinel();
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auto inputWidth = op.getInput().getType().base().getWidthOrSentinel();
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if (inputWidth <= 0)
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return failure();
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@ -3209,7 +3209,7 @@ static LogicalResult checkConnectConditionality(FConnectLike connect) {
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.Case<SubaccessOp>([&](SubaccessOp op) {
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if (op.getInput()
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.getType()
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.get()
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.base()
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.getElementTypePreservingConst()
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.isConst())
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originalFieldType = originalFieldType.getConstType(true);
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@ -4025,7 +4025,7 @@ ParseResult FEnumCreateOp::parse(OpAsmParser &parser, OperationState &result) {
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//===----------------------------------------------------------------------===//
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LogicalResult IsTagOp::verify() {
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if (getFieldIndex() >= getInput().getType().get().getNumElements())
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if (getFieldIndex() >= getInput().getType().base().getNumElements())
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return emitOpError("element index is greater than the number of fields in "
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"the bundle type");
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return success();
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@ -4214,7 +4214,7 @@ LogicalResult OpenSubfieldOp::verify() {
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}
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LogicalResult SubtagOp::verify() {
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if (getFieldIndex() >= getInput().getType().get().getNumElements())
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if (getFieldIndex() >= getInput().getType().base().getNumElements())
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return emitOpError("subfield element index is greater than the number "
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"of fields in the bundle type");
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return success();
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@ -118,17 +118,17 @@ public:
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.Case<SubindexOp>([&](SubindexOp sub) {
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recordValueRefersToFieldRef(
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sub.getInput(),
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sub.getInput().getType().get().getFieldID(sub.getIndex()),
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sub.getInput().getType().base().getFieldID(sub.getIndex()),
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sub.getResult());
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})
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.Case<SubfieldOp>([&](SubfieldOp sub) {
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recordValueRefersToFieldRef(
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sub.getInput(),
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sub.getInput().getType().get().getFieldID(sub.getFieldIndex()),
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sub.getInput().getType().base().getFieldID(sub.getFieldIndex()),
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sub.getResult());
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})
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.Case<SubaccessOp>([&](SubaccessOp sub) {
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auto vecType = sub.getInput().getType().get();
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auto vecType = sub.getInput().getType().base();
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auto input = sub.getInput();
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auto result = sub.getResult();
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// Flatten the subaccess. The result can refer to any of the
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@ -80,7 +80,7 @@ struct InferReadWritePass : public InferReadWriteBase<InferReadWritePass> {
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for (Operation *u : portVal.getUsers())
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if (auto sf = dyn_cast<SubfieldOp>(u)) {
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// Get the field name.
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auto fName = sf.getInput().getType().get().getElementName(
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auto fName = sf.getInput().getType().base().getElementName(
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sf.getFieldIndex());
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// If this is the enable field, record the product terms(the And
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// expression tree).
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@ -188,7 +188,7 @@ struct InferReadWritePass : public InferReadWriteBase<InferReadWritePass> {
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// replace them.
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for (Operation *u : portVal.getUsers())
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if (auto sf = dyn_cast<SubfieldOp>(u)) {
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StringRef fName = sf.getInput().getType().get().getElementName(
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StringRef fName = sf.getInput().getType().base().getElementName(
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sf.getFieldIndex());
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Value repl;
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if (isReadPort)
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@ -328,7 +328,7 @@ private:
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if (auto sf = dyn_cast<SubfieldOp>(u)) {
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// Get the field name.
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auto fName =
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sf.getInput().getType().get().getElementName(sf.getFieldIndex());
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sf.getInput().getType().base().getElementName(sf.getFieldIndex());
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// Check if this is the mask field.
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if (fName.contains("mask")) {
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// Already 1 bit, nothing to do.
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@ -379,7 +379,7 @@ private:
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auto sf =
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builder.create<SubfieldOp>(newPortVal, oldRes.getFieldIndex());
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auto fName =
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sf.getInput().getType().get().getElementName(sf.getFieldIndex());
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sf.getInput().getType().base().getElementName(sf.getFieldIndex());
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// Replace all mask fields with a one bit constant 1.
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// Replace all other fields with the new port.
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if (fName.contains("mask")) {
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@ -1394,7 +1394,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
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// If the constant has a known width, use that. Otherwise pick the
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// smallest number of bits necessary to represent the constant.
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Expr *e;
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if (auto width = op.getType().get().getWidth())
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if (auto width = op.getType().base().getWidth())
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e = solver.known(*width);
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else {
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auto v = op.getValue();
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@ -1496,7 +1496,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
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.Case<DivPrimOp>([&](auto op) {
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auto lhs = getExpr(op.getLhs());
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Expr *e;
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if (op.getType().get().isSigned()) {
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if (op.getType().base().isSigned()) {
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e = solver.add(lhs, solver.known(1));
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} else {
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e = lhs;
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@ -1542,7 +1542,7 @@ LogicalResult InferenceMapping::mapOperation(Operation *op) {
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})
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.Case<CvtPrimOp>([&](auto op) {
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auto input = getExpr(op.getInput());
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auto e = op.getInput().getType().get().isSigned()
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auto e = op.getInput().getType().base().isSigned()
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? input
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: solver.add(input, solver.known(1));
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setExpr(op.getResult(), e);
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@ -325,7 +325,7 @@ static SmallVector<SubfieldOp> getAllFieldAccesses(Value structValue,
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assert(isa<SubfieldOp>(op));
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auto fieldAccess = cast<SubfieldOp>(op);
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auto elemIndex =
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fieldAccess.getInput().getType().get().getElementIndex(field);
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fieldAccess.getInput().getType().base().getElementIndex(field);
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if (elemIndex && *elemIndex == fieldAccess.getFieldIndex())
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accesses.push_back(fieldAccess);
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}
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@ -234,7 +234,7 @@ static bool isNotSubAccess(Operation *op) {
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return true;
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ConstantOp arg =
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llvm::dyn_cast_or_null<ConstantOp>(sao.getIndex().getDefiningOp());
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return arg && sao.getInput().getType().get().getNumElements() != 0;
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return arg && sao.getInput().getType().base().getNumElements() != 0;
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}
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/// Look through and collect subfields leading to a subaccess.
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@ -846,7 +846,8 @@ LogicalResult Visitor::visitExpr(VectorCreateOp op) {
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}
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auto value = sinkVecDimIntoOperands(
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builder, convertType(oldType.get().getElementType()), convertedOldFields);
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builder, convertType(oldType.base().getElementType()),
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convertedOldFields);
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valueMap[op.getResult()] = value;
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toDelete.push_back(op);
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return success();
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