mirror of https://github.com/llvm/circt.git
[Ibis] Add ibistool (#6206)
Adds `ibistool` - a tool for driving Ibis lowerings. The tool has two modes - low-level and high-level Ibis lowering. Alongside this, introduce a set of Ibis pass pipelines which other users may load to ensure that they're lowering ibis constructs in the standard order.
This commit is contained in:
Morten Borup Petersen
GitHub
parent
c8ab1e1163
commit
6b73873825
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//===- IbisPassPipelines.h - Ibis pass pipelines -----------------*- C++-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_DIALECT_IBIS_IBISPASSPIPELINES_H
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#define CIRCT_DIALECT_IBIS_IBISPASSPIPELINES_H
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#include "circt/Dialect/Ibis/IbisPasses.h"
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#include "mlir/Pass/PassManager.h"
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#include <memory>
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#include <optional>
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namespace circt {
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namespace ibis {
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// Loads a pass pipeline to transform low-level Ibis constructs.
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void loadIbisLowLevelPassPipeline(mlir::PassManager &pm);
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// Loads a pass pipeline to transform high-level Ibis constructs.
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void loadIbisHighLevelPassPipeline(mlir::PassManager &pm);
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} // namespace ibis
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} // namespace circt
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#endif // CIRCT_DIALECT_IBIS_IBISPASSPIPELINES_H
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@ -21,16 +21,17 @@ namespace ibis {
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#define GEN_PASS_DECL_IBISTUNNELING
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#define GEN_PASS_DECL_IBISTUNNELING
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#include "circt/Dialect/Ibis/IbisPasses.h.inc"
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#include "circt/Dialect/Ibis/IbisPasses.h.inc"
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std::unique_ptr<Pass> createCallPrepPass();
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std::unique_ptr<mlir::Pass> createCallPrepPass();
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std::unique_ptr<Pass> createContainerizePass();
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std::unique_ptr<mlir::Pass> createContainerizePass();
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std::unique_ptr<Pass> createTunnelingPass(const IbisTunnelingOptions & = {});
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std::unique_ptr<mlir::Pass>
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std::unique_ptr<Pass> createPortrefLoweringPass();
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createTunnelingPass(const IbisTunnelingOptions & = {});
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std::unique_ptr<Pass> createCleanSelfdriversPass();
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std::unique_ptr<mlir::Pass> createPortrefLoweringPass();
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std::unique_ptr<Pass> createContainersToHWPass();
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std::unique_ptr<mlir::Pass> createCleanSelfdriversPass();
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std::unique_ptr<Pass> createArgifyBlocksPass();
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std::unique_ptr<mlir::Pass> createContainersToHWPass();
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std::unique_ptr<Pass> createReblockPass();
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std::unique_ptr<mlir::Pass> createArgifyBlocksPass();
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std::unique_ptr<Pass> createInlineSBlocksPass();
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std::unique_ptr<mlir::Pass> createReblockPass();
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std::unique_ptr<Pass> createConvertCFToHandshakePass();
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std::unique_ptr<mlir::Pass> createInlineSBlocksPass();
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std::unique_ptr<mlir::Pass> createConvertCFToHandshakePass();
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/// Generate the code for registering passes.
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/// Generate the code for registering passes.
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#define GEN_PASS_REGISTRATION
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#define GEN_PASS_REGISTRATION
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@ -10,6 +10,7 @@ set(CIRCT_INTEGRATION_TEST_DEPENDS
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esi-collateral
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esi-collateral
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firtool
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firtool
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hlstool
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hlstool
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ibistool
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handshake-runner
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handshake-runner
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)
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)
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@ -1,8 +1,4 @@
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// RUN: circt-opt --ibis-containerize --ibis-tunneling --ibis-lower-portrefs \
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// RUN: ibistool -lo %s
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// RUN: --canonicalize --ibis-clean-selfdrivers --canonicalize \
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// RUN: --ibis-convert-containers-to-hw --pipeline-explicit-regs \
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// RUN: --lower-pipeline-to-hw --lower-seq-to-sv \
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// RUN: --export-verilog -o %t_lo.mlir %s > %t.sv
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// A class hierarchy with a shared parent, and accessing between the children
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// A class hierarchy with a shared parent, and accessing between the children
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@ -9,6 +9,7 @@ add_circt_dialect_library(CIRCTIbisTransforms
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IbisReblockPass.cpp
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IbisReblockPass.cpp
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IbisInlineSBlocksPass.cpp
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IbisInlineSBlocksPass.cpp
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IbisConvertCFToHandshake.cpp
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IbisConvertCFToHandshake.cpp
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IbisPassPipelines.cpp
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DEPENDS
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DEPENDS
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CIRCTIbisTransformsIncGen
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CIRCTIbisTransformsIncGen
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//===- IbisPassPipelines.cpp - Ibis pass pipelines ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/Ibis/IbisPassPipelines.h"
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#include "circt/Dialect/Ibis/IbisOps.h"
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#include "circt/Transforms/Passes.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "mlir/Transforms/Passes.h"
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using namespace mlir;
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using namespace circt;
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using namespace ibis;
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/// Create a simple canonicalizer pass.
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static std::unique_ptr<Pass> createSimpleCanonicalizerPass() {
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mlir::GreedyRewriteConfig config;
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config.useTopDownTraversal = true;
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config.enableRegionSimplification = false;
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return mlir::createCanonicalizerPass(config);
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}
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void circt::ibis::loadIbisLowLevelPassPipeline(mlir::PassManager &pm) {
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pm.addPass(createContainerizePass());
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pm.addPass(createTunnelingPass(IbisTunnelingOptions{"", ""}));
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pm.addPass(createPortrefLoweringPass());
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pm.addPass(createSimpleCanonicalizerPass());
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pm.addPass(createCleanSelfdriversPass());
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pm.addPass(createContainersToHWPass());
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}
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void circt::ibis::loadIbisHighLevelPassPipeline(mlir::PassManager &pm) {
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pm.nest<ibis::MethodOp>().addPass(ibis::createInlineSBlocksPass());
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pm.addPass(mlir::createMem2Reg());
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// TODO @mortbopet: Add a verification pass to ensure that there are no more
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// memref.alloca's - we want all memories to be mem2reg'able, unless they are
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// member variable accesses.
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// - just add it as an illegal op.
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// Now, perform SSA maximizations.
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pm.addPass(circt::createMaximizeSSAPass());
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// SSA maximal form achieved. Reconstruct the Ibis sblocks.
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pm.nest<ibis::MethodOp>().addPass(ibis::createReblockPass());
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pm.addPass(ibis::createArgifyBlocksPass());
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pm.addPass(createSimpleCanonicalizerPass());
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// Make the CFG a binary tree by inserting merge blocks.
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pm.addPass(circt::createInsertMergeBlocksPass());
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// Perform dataflow conversion
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pm.nest<ibis::ClassOp>().addPass(ibis::createConvertCFToHandshakePass());
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// Canonicalize - necessary after handshake conversion to clean up a lot of
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// stuff e.g. simple branches.
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pm.addPass(createSimpleCanonicalizerPass());
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}
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@ -29,6 +29,7 @@ set(CIRCT_TEST_DEPENDS
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handshake-runner
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handshake-runner
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firtool
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firtool
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hlstool
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hlstool
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ibistool
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om-linker
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om-linker
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)
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)
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@ -0,0 +1,66 @@
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// RUN: ibistool --hi --post-ibis-ir %s | FileCheck %s
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// CHECK-LABEL: ibis.class @ToHandshake {
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// CHECK: %[[VAL_0:.*]] = ibis.this @ToHandshake
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// CHECK: ibis.method.df @foo(%[[VAL_1:.*]]: index, %[[VAL_2:.*]]: index, %[[VAL_3:.*]]: i1, %[[VAL_4:.*]]: none) -> (i32, none) {
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// CHECK: %[[VAL_5:.*]] = handshake.constant %[[VAL_4]] {value = 2 : i32} : i32
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// CHECK: %[[VAL_6:.*]] = handshake.constant %[[VAL_4]] {value = 1 : index} : index
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// CHECK: %[[VAL_7:.*]] = handshake.constant %[[VAL_4]] {value = 0 : i32} : i32
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// CHECK: %[[VAL_8:.*]] = handshake.buffer [1] seq %[[VAL_9:.*]] {initValues = [0]} : i1
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// CHECK: %[[VAL_10:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_4]], %[[VAL_11:.*]]] : i1, none
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// CHECK: %[[VAL_12:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_1]], %[[VAL_13:.*]]] : i1, index
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// CHECK: %[[VAL_14:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_7]], %[[VAL_15:.*]]] : i1, i32
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// CHECK: %[[VAL_16:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_2]], %[[VAL_17:.*]]] : i1, index
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// CHECK: %[[VAL_18:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_5]], %[[VAL_19:.*]]] : i1, i32
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// CHECK: %[[VAL_20:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_6]], %[[VAL_21:.*]]] : i1, index
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// CHECK: %[[VAL_22:.*]] = handshake.mux %[[VAL_8]] {{\[}}%[[VAL_7]], %[[VAL_23:.*]]] : i1, i32
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// CHECK: %[[VAL_9]] = arith.cmpi slt, %[[VAL_12]], %[[VAL_16]] : index
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// CHECK: %[[VAL_24:.*]], %[[VAL_25:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_12]] : index
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// CHECK: %[[VAL_26:.*]], %[[VAL_27:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_14]] : i32
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// CHECK: %[[VAL_17]], %[[VAL_28:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_16]] : index
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// CHECK: %[[VAL_19]], %[[VAL_29:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_18]] : i32
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// CHECK: %[[VAL_21]], %[[VAL_30:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_20]] : index
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// CHECK: %[[VAL_23]], %[[VAL_31:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_22]] : i32
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// CHECK: %[[VAL_32:.*]], %[[VAL_33:.*]] = handshake.cond_br %[[VAL_9]], %[[VAL_10]] : none
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// CHECK: %[[VAL_34:.*]] = arith.index_cast %[[VAL_24]] : index to i32
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// CHECK: %[[VAL_35:.*]] = arith.remsi %[[VAL_26]], %[[VAL_19]] : i32
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// CHECK: %[[VAL_36:.*]] = arith.cmpi eq, %[[VAL_35]], %[[VAL_23]] : i32
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// CHECK: %[[VAL_37:.*]], %[[VAL_38:.*]] = handshake.cond_br %[[VAL_36]], %[[VAL_26]] : i32
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// CHECK: %[[VAL_39:.*]], %[[VAL_40:.*]] = handshake.cond_br %[[VAL_36]], %[[VAL_32]] : none
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// CHECK: %[[VAL_41:.*]], %[[VAL_42:.*]] = handshake.cond_br %[[VAL_36]], %[[VAL_34]] : i32
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// CHECK: %[[VAL_43:.*]] = arith.addi %[[VAL_37]], %[[VAL_41]] : i32
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// CHECK: %[[VAL_44:.*]] = arith.subi %[[VAL_38]], %[[VAL_42]] : i32
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// CHECK: %[[VAL_15]] = handshake.mux %[[VAL_45:.*]] {{\[}}%[[VAL_44]], %[[VAL_43]]] : index, i32
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// CHECK: %[[VAL_11]], %[[VAL_45]] = handshake.control_merge %[[VAL_40]], %[[VAL_39]] : none, index
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// CHECK: %[[VAL_13]] = arith.addi %[[VAL_24]], %[[VAL_21]] : index
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// CHECK: ibis.return %[[VAL_27]], %[[VAL_33]] : i32, none
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// CHECK: }
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// CHECK: }
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ibis.class @ToHandshake {
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%this = ibis.this @ToHandshake
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ibis.method @foo(%a: index, %b: index, %c : i1) -> i32 {
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%sum = memref.alloca () : memref<i32>
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%c0_i32 = arith.constant 0 : i32
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memref.store %c0_i32, %sum[] : memref<i32>
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%c1 = arith.constant 1 : index
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%c2 = arith.constant 2 : i32
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%c0 = arith.constant 0 : i32
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scf.for %i = %a to %b step %c1 {
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%acc = memref.load %sum[] : memref<i32>
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%i_i32 = arith.index_cast %i : index to i32
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%rem = arith.remsi %acc, %c2 : i32
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%cond = arith.cmpi eq, %rem, %c0 : i32
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%res = scf.if %cond -> (i32) {
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%v = arith.addi %acc, %i_i32 : i32
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scf.yield %v : i32
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} else {
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%v = arith.subi %acc, %i_i32 : i32
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scf.yield %v : i32
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}
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memref.store %res, %sum[] : memref<i32>
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}
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%res = memref.load %sum[] : memref<i32>
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ibis.return %res : i32
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}
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}
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@ -0,0 +1,75 @@
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// RUN: ibistool %s --lo --post-ibis-ir | FileCheck %s --check-prefix=CHECK-POST-IBIS
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// RUN: ibistool %s --lo --ir | FileCheck %s --check-prefix=CHECK-IR
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// RUN: ibistool %s --lo --verilog | FileCheck %s --check-prefix=CHECK-VERILOG
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// CHECK-POST-IBIS-LABEL: hw.module @A_B(
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// CHECK-POST-IBIS-SAME: %[[VAL_0:.*]]: !seq.clock, %[[VAL_1:.*]]: i1) -> (p_out: i1) {
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// CHECK-POST-IBIS: %[[VAL_2:.*]] = seq.compreg %[[VAL_1]], %[[VAL_0]] : i1
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// CHECK-POST-IBIS: hw.output %[[VAL_2]] : i1
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// CHECK-POST-IBIS: }
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// CHECK-POST-IBIS-LABEL: hw.module @A(
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// CHECK-POST-IBIS-SAME: %[[VAL_0:.*]]: i1, %[[VAL_1:.*]]: !seq.clock) -> (out: i1) {
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// CHECK-POST-IBIS: %[[VAL_2:.*]] = hw.instance "A_B" @A_B(p_clk: %[[VAL_1]]: !seq.clock, p_in: %[[VAL_0]]: i1) -> (p_out: i1)
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// CHECK-POST-IBIS: hw.output %[[VAL_2]] : i1
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// CHECK-POST-IBIS: }
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// CHECK-IR-LABEL: hw.module @A_B(
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// CHECK-IR-SAME: %[[VAL_0:.*]]: i1, %[[VAL_1:.*]]: i1) -> (p_out: i1) {
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// CHECK-IR: %[[VAL_2:.*]] = sv.reg : !hw.inout<i1>
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// CHECK-IR: %[[VAL_3:.*]] = sv.read_inout %[[VAL_2]] : !hw.inout<i1>
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// CHECK-IR: sv.alwaysff(posedge %[[VAL_0]]) {
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// CHECK-IR: sv.passign %[[VAL_2]], %[[VAL_1]] : i1
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// CHECK-IR: }
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// CHECK-IR: hw.output %[[VAL_3]] : i1
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// CHECK-IR: }
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// CHECK-IR-LABEL: hw.module @A(
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// CHECK-IR-SAME: %[[VAL_0:.*]]: i1, %[[VAL_1:.*]]: i1) -> (out: i1) {
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// CHECK-IR: %[[VAL_2:.*]] = hw.instance "A_B" @A_B(p_clk: %[[VAL_1]]: i1, p_in: %[[VAL_0]]: i1) -> (p_out: i1)
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// CHECK-IR: hw.output %[[VAL_2]] : i1
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// CHECK-IR: }
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// CHECK-VERILOG-LABEL: module A_B(
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// CHECK-VERILOG: input p_clk,
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// CHECK-VERILOG: p_in,
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// CHECK-VERILOG: output p_out
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// CHECK-VERILOG: );
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// CHECK-VERILOG: reg r;
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// CHECK-VERILOG: always_ff @(posedge p_clk)
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// CHECK-VERILOG: r <= p_in;
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// CHECK-VERILOG: assign p_out = r;
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// CHECK-VERILOG: endmodule
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// CHECK-VERILOG-LABEL: module A(
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// CHECK-VERILOG: input in,
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// CHECK-VERILOG: clk,
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// CHECK-VERILOG: output out
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// CHECK-VERILOG: );
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// CHECK-VERILOG: A_B A_B (
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// CHECK-VERILOG: .p_clk (clk),
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// CHECK-VERILOG: .p_in (in),
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// CHECK-VERILOG: .p_out (out)
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// CHECK-VERILOG: );
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// CHECK-VERILOG: endmodule
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ibis.class @A {
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%this = ibis.this @A
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ibis.port.input @in : i1
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||||||
|
ibis.port.output @out : i1
|
||||||
|
ibis.port.input @clk : !seq.clock
|
||||||
|
|
||||||
|
ibis.container@B {
|
||||||
|
%B_this = ibis.this @B
|
||||||
|
%parent = ibis.path [
|
||||||
|
#ibis.step<parent : !ibis.scoperef<@A>>
|
||||||
|
]
|
||||||
|
%a_in = ibis.get_port %parent, @in : !ibis.scoperef<@A> -> !ibis.portref<out i1>
|
||||||
|
%a_clk = ibis.get_port %parent, @clk : !ibis.scoperef<@A> -> !ibis.portref<out !seq.clock>
|
||||||
|
%a_out = ibis.get_port %parent, @out : !ibis.scoperef<@A> -> !ibis.portref<in i1>
|
||||||
|
%in = ibis.port.read %a_in : !ibis.portref<out i1>
|
||||||
|
%clk = ibis.port.read %a_clk : !ibis.portref<out !seq.clock>
|
||||||
|
%r = seq.compreg %in, %clk: i1
|
||||||
|
ibis.port.write %a_out, %r : !ibis.portref<in i1>
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -58,7 +58,7 @@ tool_dirs = [
|
||||||
tools = [
|
tools = [
|
||||||
'arcilator', 'circt-as', 'circt-capi-ir-test', 'circt-capi-om-test',
|
'arcilator', 'circt-as', 'circt-capi-ir-test', 'circt-capi-om-test',
|
||||||
'circt-capi-firrtl-test', 'circt-dis', 'circt-opt', 'circt-reduce',
|
'circt-capi-firrtl-test', 'circt-dis', 'circt-opt', 'circt-reduce',
|
||||||
'circt-translate', 'firtool', 'hlstool', 'om-linker'
|
'circt-translate', 'firtool', 'hlstool', 'om-linker', 'ibistool'
|
||||||
]
|
]
|
||||||
|
|
||||||
# Enable Verilator if it has been detected.
|
# Enable Verilator if it has been detected.
|
||||||
|
|
|
||||||
|
|
@ -15,3 +15,4 @@ add_subdirectory(llhd-sim)
|
||||||
add_subdirectory(om-linker)
|
add_subdirectory(om-linker)
|
||||||
add_subdirectory(py-split-input-file)
|
add_subdirectory(py-split-input-file)
|
||||||
add_subdirectory(hlstool)
|
add_subdirectory(hlstool)
|
||||||
|
add_subdirectory(ibistool)
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
set(LLVM_LINK_COMPONENTS
|
||||||
|
Support
|
||||||
|
)
|
||||||
|
|
||||||
|
add_circt_tool(ibistool
|
||||||
|
ibistool.cpp
|
||||||
|
)
|
||||||
|
llvm_update_compile_flags(ibistool)
|
||||||
|
target_link_libraries(ibistool
|
||||||
|
PRIVATE
|
||||||
|
|
||||||
|
CIRCTExportChiselInterface
|
||||||
|
CIRCTExportVerilog
|
||||||
|
CIRCTHandshake
|
||||||
|
CIRCTHandshakeToHW
|
||||||
|
CIRCTHandshakeTransforms
|
||||||
|
CIRCTHW
|
||||||
|
CIRCTHWTransforms
|
||||||
|
CIRCTSeq
|
||||||
|
CIRCTSeqToSV
|
||||||
|
CIRCTSeqTransforms
|
||||||
|
CIRCTCFToHandshake
|
||||||
|
CIRCTSV
|
||||||
|
CIRCTSVTransforms
|
||||||
|
CIRCTIbis
|
||||||
|
CIRCTIbisTransforms
|
||||||
|
CIRCTTransforms
|
||||||
|
CIRCTPipelineOps
|
||||||
|
CIRCTPipelineToHW
|
||||||
|
CIRCTDCToHW
|
||||||
|
CIRCTHandshakeToDC
|
||||||
|
|
||||||
|
CIRCTPipelineTransforms
|
||||||
|
CIRCTDC
|
||||||
|
CIRCTDCTransforms
|
||||||
|
CIRCTESI
|
||||||
|
|
||||||
|
MLIRIR
|
||||||
|
MLIRLLVMDialect
|
||||||
|
MLIRMemRefDialect
|
||||||
|
MLIROptLib
|
||||||
|
MLIRParser
|
||||||
|
MLIRControlFlowDialect
|
||||||
|
MLIRSupport
|
||||||
|
MLIRTransforms
|
||||||
|
MLIRSCFToControlFlow
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,434 @@
|
||||||
|
//===- ibistool.cpp - The ibistool utility for working with the Ibis dialect =//
|
||||||
|
//
|
||||||
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||||
|
// See https://llvm.org/LICENSE.txt for license information.
|
||||||
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file implements 'ibistool', which composes together a variety of
|
||||||
|
// CIRCT libraries that can be used to realise an Ibis-based lowering flow.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
#include "mlir/Conversion/Passes.h"
|
||||||
|
#include "mlir/Dialect/Affine/IR/AffineOps.h"
|
||||||
|
#include "mlir/Dialect/Arith/IR/Arith.h"
|
||||||
|
#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
|
||||||
|
#include "mlir/Dialect/Func/IR/FuncOps.h"
|
||||||
|
#include "mlir/Dialect/MemRef/IR/MemRef.h"
|
||||||
|
#include "mlir/IR/AsmState.h"
|
||||||
|
#include "mlir/IR/BuiltinOps.h"
|
||||||
|
#include "mlir/Parser/Parser.h"
|
||||||
|
#include "mlir/Pass/Pass.h"
|
||||||
|
#include "mlir/Pass/PassInstrumentation.h"
|
||||||
|
#include "mlir/Pass/PassManager.h"
|
||||||
|
#include "mlir/Support/FileUtilities.h"
|
||||||
|
#include "mlir/Support/Timing.h"
|
||||||
|
#include "mlir/Support/ToolUtilities.h"
|
||||||
|
#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
|
||||||
|
#include "mlir/Transforms/Passes.h"
|
||||||
|
|
||||||
|
#include "llvm/Support/Chrono.h"
|
||||||
|
#include "llvm/Support/CommandLine.h"
|
||||||
|
#include "llvm/Support/FileSystem.h"
|
||||||
|
#include "llvm/Support/InitLLVM.h"
|
||||||
|
#include "llvm/Support/Path.h"
|
||||||
|
#include "llvm/Support/SourceMgr.h"
|
||||||
|
#include "llvm/Support/ToolOutputFile.h"
|
||||||
|
|
||||||
|
#include "circt/Conversion/ExportVerilog.h"
|
||||||
|
#include "circt/Conversion/Passes.h"
|
||||||
|
#include "circt/Dialect/DC/DCDialect.h"
|
||||||
|
#include "circt/Dialect/DC/DCPasses.h"
|
||||||
|
#include "circt/Dialect/ESI/ESIDialect.h"
|
||||||
|
#include "circt/Dialect/ESI/ESIPasses.h"
|
||||||
|
#include "circt/Dialect/Ibis/IbisDialect.h"
|
||||||
|
#include "circt/Dialect/Ibis/IbisPassPipelines.h"
|
||||||
|
#include "circt/Dialect/Ibis/IbisPasses.h"
|
||||||
|
#include "circt/Dialect/Pipeline/PipelineDialect.h"
|
||||||
|
#include "circt/Dialect/Pipeline/PipelinePasses.h"
|
||||||
|
#include "circt/Dialect/SV/SVDialect.h"
|
||||||
|
#include "circt/Dialect/SV/SVPasses.h"
|
||||||
|
#include "circt/Dialect/Seq/SeqDialect.h"
|
||||||
|
#include "circt/Dialect/Seq/SeqPasses.h"
|
||||||
|
#include "circt/Support/LoweringOptions.h"
|
||||||
|
#include "circt/Support/LoweringOptionsParser.h"
|
||||||
|
#include "circt/Support/Version.h"
|
||||||
|
#include "circt/Transforms/Passes.h"
|
||||||
|
|
||||||
|
#include <iostream>
|
||||||
|
|
||||||
|
using namespace llvm;
|
||||||
|
using namespace mlir;
|
||||||
|
using namespace circt;
|
||||||
|
using namespace ibis;
|
||||||
|
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
// Tool options
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
|
||||||
|
static cl::OptionCategory mainCategory("ibistool Options");
|
||||||
|
|
||||||
|
static cl::opt<std::string> inputFilename(cl::Positional,
|
||||||
|
cl::desc("<input file>"),
|
||||||
|
cl::init("-"), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<std::string> outputFilename(
|
||||||
|
"o", cl::desc("Output filename, or directory for split output"),
|
||||||
|
cl::value_desc("filename"), cl::init("-"), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
splitInputFile("split-input-file",
|
||||||
|
cl::desc("Split the input file into pieces and process each "
|
||||||
|
"chunk independently"),
|
||||||
|
cl::init(false), cl::Hidden, cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
verifyDiagnostics("verify-diagnostics",
|
||||||
|
cl::desc("Check that emitted diagnostics match "
|
||||||
|
"expected-* lines on the corresponding line"),
|
||||||
|
cl::init(false), cl::Hidden, cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
verbosePassExecutions("verbose-pass-executions",
|
||||||
|
cl::desc("Log executions of toplevel module passes"),
|
||||||
|
cl::init(false), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
verifyPasses("verify-each",
|
||||||
|
cl::desc("Run the verifier after each transformation pass"),
|
||||||
|
cl::init(true), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
allowUnregisteredDialects("allow-unregistered-dialects",
|
||||||
|
cl::desc("Allow unknown dialects in the input"),
|
||||||
|
cl::init(false), cl::Hidden,
|
||||||
|
cl::cat(mainCategory));
|
||||||
|
|
||||||
|
enum OutputFormatKind {
|
||||||
|
OutputLoweredIbis,
|
||||||
|
OutputIR,
|
||||||
|
OutputVerilog,
|
||||||
|
OutputSplitVerilog
|
||||||
|
};
|
||||||
|
|
||||||
|
static cl::opt<OutputFormatKind> outputFormat(
|
||||||
|
cl::desc("Specify output format:"),
|
||||||
|
cl::values(
|
||||||
|
clEnumValN(OutputLoweredIbis, "post-ibis-ir",
|
||||||
|
"Emit IR after Ibis constructs have been lowered away"),
|
||||||
|
clEnumValN(OutputIR, "ir", "Emit pre-emission IR"),
|
||||||
|
clEnumValN(OutputVerilog, "verilog", "Emit Verilog"),
|
||||||
|
clEnumValN(OutputSplitVerilog, "split-verilog",
|
||||||
|
"Emit Verilog (one file per module; specify "
|
||||||
|
"directory with -o=<dir>)")),
|
||||||
|
cl::init(OutputVerilog), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
traceIVerilog("sv-trace-iverilog",
|
||||||
|
cl::desc("Add tracing to an iverilog simulated module"),
|
||||||
|
cl::init(false), cl::cat(mainCategory));
|
||||||
|
|
||||||
|
enum FlowKind { HiIbis, LoIbis };
|
||||||
|
static cl::opt<FlowKind>
|
||||||
|
flowKind(cl::desc("Specify flow kind:"),
|
||||||
|
cl::values(clEnumValN(HiIbis, "hi", "High-level Ibis flow"),
|
||||||
|
clEnumValN(LoIbis, "lo", "Low-level Ibis flow")),
|
||||||
|
cl::Required, cl::cat(mainCategory));
|
||||||
|
|
||||||
|
static LoweringOptionsOption loweringOptions(mainCategory);
|
||||||
|
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
// (Configurable) pass pipelines
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
|
||||||
|
/// Create a simple canonicalizer pass.
|
||||||
|
static std::unique_ptr<Pass> createSimpleCanonicalizerPass() {
|
||||||
|
mlir::GreedyRewriteConfig config;
|
||||||
|
config.useTopDownTraversal = true;
|
||||||
|
config.enableRegionSimplification = false;
|
||||||
|
return mlir::createCanonicalizerPass(config);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadHighLevelControlflowTransformsPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(mlir::createLowerAffinePass());
|
||||||
|
pm.addPass(mlir::createConvertSCFToCFPass());
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadHandshakeTransformsPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(circt::createCFToHandshakePass(
|
||||||
|
/*sourceConstants=*/false,
|
||||||
|
/*disableTaskPipelining=*/false));
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
pm.nest<handshake::FuncOp>().addPass(
|
||||||
|
handshake::createHandshakeMaterializeForksSinksPass());
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
pm.nest<handshake::FuncOp>().addPass(
|
||||||
|
handshake::createHandshakeInsertBuffersPass("all", 2));
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadDCTransformsPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(circt::createHandshakeToDCPass());
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
pm.addPass(circt::createDCToHWPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadESILoweringPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(circt::esi::createESIPortLoweringPass());
|
||||||
|
pm.addPass(circt::esi::createESIPhysicalLoweringPass());
|
||||||
|
pm.addPass(circt::esi::createESItoHWPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadHWLoweringPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
pm.nest<hw::HWModuleOp>().addPass(circt::seq::createLowerSeqHLMemPass());
|
||||||
|
pm.addPass(sv::createHWMemSimImplPass(false, false));
|
||||||
|
pm.addPass(circt::createLowerSeqToSVPass());
|
||||||
|
pm.nest<hw::HWModuleOp>().addPass(sv::createHWCleanupPass());
|
||||||
|
pm.addPass(mlir::createCSEPass());
|
||||||
|
|
||||||
|
// Legalize unsupported operations within the modules.
|
||||||
|
pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
|
||||||
|
// Tidy up the IR to improve verilog emission quality.
|
||||||
|
auto &modulePM = pm.nest<hw::HWModuleOp>();
|
||||||
|
modulePM.addPass(sv::createPrettifyVerilogPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadPipelineLoweringPipeline(OpPassManager &pm) {
|
||||||
|
pm.addPass(pipeline::createExplicitRegsPass());
|
||||||
|
pm.addPass(createPipelineToHWPass());
|
||||||
|
}
|
||||||
|
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
// Tool driver code
|
||||||
|
// --------------------------------------------------------------------------
|
||||||
|
|
||||||
|
static void loadLowLevelPassPipeline(
|
||||||
|
PassManager &pm, ModuleOp module,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
loadPipelineLoweringPipeline(pm);
|
||||||
|
loadESILoweringPipeline(pm);
|
||||||
|
loadHWLoweringPipeline(pm);
|
||||||
|
if (traceIVerilog)
|
||||||
|
pm.addPass(circt::sv::createSVTraceIVerilogPass());
|
||||||
|
|
||||||
|
if (loweringOptions.getNumOccurrences())
|
||||||
|
loweringOptions.setAsAttribute(module);
|
||||||
|
if (outputFormat == OutputVerilog) {
|
||||||
|
pm.addPass(createExportVerilogPass((*outputFile)->os()));
|
||||||
|
} else if (outputFormat == OutputSplitVerilog) {
|
||||||
|
pm.addPass(createExportSplitVerilogPass(outputFilename));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadIbisHiFlow(
|
||||||
|
PassManager &pm, ModuleOp module,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
if (verbosePassExecutions)
|
||||||
|
llvm::errs() << "[ibistool] Will run high-level Ibis flow\n";
|
||||||
|
|
||||||
|
loadHighLevelControlflowTransformsPipeline(pm);
|
||||||
|
loadIbisHighLevelPassPipeline(pm);
|
||||||
|
if (outputFormat != OutputLoweredIbis) {
|
||||||
|
loadHandshakeTransformsPipeline(pm);
|
||||||
|
loadDCTransformsPipeline(pm);
|
||||||
|
if (outputFormat != OutputLoweredIbis)
|
||||||
|
loadLowLevelPassPipeline(pm, module, outputFile);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void loadIbisLoFlow(
|
||||||
|
PassManager &pm, ModuleOp module,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
if (verbosePassExecutions)
|
||||||
|
llvm::errs() << "[ibistool] Will run low-level Ibis flow\n";
|
||||||
|
loadIbisLowLevelPassPipeline(pm);
|
||||||
|
|
||||||
|
if (outputFormat != OutputLoweredIbis)
|
||||||
|
loadLowLevelPassPipeline(pm, module, outputFile);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Process a single buffer of the input.
|
||||||
|
static LogicalResult processBuffer(
|
||||||
|
MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
// Parse the input.
|
||||||
|
mlir::OwningOpRef<mlir::ModuleOp> module;
|
||||||
|
llvm::sys::TimePoint<> parseStartTime;
|
||||||
|
if (verbosePassExecutions) {
|
||||||
|
llvm::errs() << "[ibistool] Running MLIR parser\n";
|
||||||
|
parseStartTime = llvm::sys::TimePoint<>::clock::now();
|
||||||
|
}
|
||||||
|
auto parserTimer = ts.nest("MLIR Parser");
|
||||||
|
module = parseSourceFile<ModuleOp>(sourceMgr, &context);
|
||||||
|
|
||||||
|
if (!module)
|
||||||
|
return failure();
|
||||||
|
|
||||||
|
if (verbosePassExecutions) {
|
||||||
|
auto elpased = std::chrono::duration<double>(
|
||||||
|
llvm::sys::TimePoint<>::clock::now() - parseStartTime) /
|
||||||
|
std::chrono::seconds(1);
|
||||||
|
llvm::errs() << "[ibistool] -- Done in " << llvm::format("%.3f", elpased)
|
||||||
|
<< " sec\n";
|
||||||
|
}
|
||||||
|
|
||||||
|
// Apply any pass manager command line options.
|
||||||
|
PassManager pm(&context);
|
||||||
|
pm.enableVerifier(verifyPasses);
|
||||||
|
pm.enableTiming(ts);
|
||||||
|
if (failed(applyPassManagerCLOptions(pm)))
|
||||||
|
return failure();
|
||||||
|
|
||||||
|
pm.addPass(createSimpleCanonicalizerPass());
|
||||||
|
if (flowKind == HiIbis)
|
||||||
|
loadIbisHiFlow(pm, module.get(), outputFile);
|
||||||
|
else if (flowKind == LoIbis)
|
||||||
|
loadIbisLoFlow(pm, module.get(), outputFile);
|
||||||
|
|
||||||
|
// Go execute!
|
||||||
|
if (failed(pm.run(module.get())))
|
||||||
|
return failure();
|
||||||
|
if (outputFormat != OutputVerilog || outputFormat == OutputSplitVerilog)
|
||||||
|
module->print((*outputFile)->os());
|
||||||
|
|
||||||
|
return success();
|
||||||
|
|
||||||
|
// We intentionally "leak" the Module into the MLIRContext instead of
|
||||||
|
// deallocating it. There is no need to deallocate it right before process
|
||||||
|
// exit.
|
||||||
|
(void)module.release();
|
||||||
|
return success();
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Process a single split of the input. This allocates a source manager and
|
||||||
|
/// creates a regular or verifying diagnostic handler, depending on whether
|
||||||
|
/// the user set the verifyDiagnostics option.
|
||||||
|
static LogicalResult processInputSplit(
|
||||||
|
MLIRContext &context, TimingScope &ts,
|
||||||
|
std::unique_ptr<llvm::MemoryBuffer> buffer,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
llvm::SourceMgr sourceMgr;
|
||||||
|
sourceMgr.AddNewSourceBuffer(std::move(buffer), llvm::SMLoc());
|
||||||
|
if (!verifyDiagnostics) {
|
||||||
|
SourceMgrDiagnosticHandler sourceMgrHandler(sourceMgr, &context);
|
||||||
|
return processBuffer(context, ts, sourceMgr, outputFile);
|
||||||
|
}
|
||||||
|
|
||||||
|
SourceMgrDiagnosticVerifierHandler sourceMgrHandler(sourceMgr, &context);
|
||||||
|
context.printOpOnDiagnostic(false);
|
||||||
|
(void)processBuffer(context, ts, sourceMgr, outputFile);
|
||||||
|
return sourceMgrHandler.verify();
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Process the entire input provided by the user, splitting it up if the
|
||||||
|
/// corresponding option was specified.
|
||||||
|
static LogicalResult
|
||||||
|
processInput(MLIRContext &context, TimingScope &ts,
|
||||||
|
std::unique_ptr<llvm::MemoryBuffer> input,
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> &outputFile) {
|
||||||
|
if (!splitInputFile)
|
||||||
|
return processInputSplit(context, ts, std::move(input), outputFile);
|
||||||
|
|
||||||
|
return splitAndProcessBuffer(
|
||||||
|
std::move(input),
|
||||||
|
[&](std::unique_ptr<MemoryBuffer> buffer, raw_ostream &) {
|
||||||
|
return processInputSplit(context, ts, std::move(buffer), outputFile);
|
||||||
|
},
|
||||||
|
llvm::outs());
|
||||||
|
}
|
||||||
|
|
||||||
|
static LogicalResult executeIbistool(MLIRContext &context) {
|
||||||
|
if (allowUnregisteredDialects)
|
||||||
|
context.allowUnregisteredDialects();
|
||||||
|
|
||||||
|
// Create the timing manager we use to sample execution times.
|
||||||
|
DefaultTimingManager tm;
|
||||||
|
applyDefaultTimingManagerCLOptions(tm);
|
||||||
|
auto ts = tm.getRootScope();
|
||||||
|
|
||||||
|
// Set up the input file.
|
||||||
|
std::string errorMessage;
|
||||||
|
auto input = openInputFile(inputFilename, &errorMessage);
|
||||||
|
if (!input) {
|
||||||
|
llvm::errs() << errorMessage << "\n";
|
||||||
|
return failure();
|
||||||
|
}
|
||||||
|
|
||||||
|
std::optional<std::unique_ptr<llvm::ToolOutputFile>> outputFile;
|
||||||
|
if (outputFormat != OutputSplitVerilog) {
|
||||||
|
outputFile.emplace(openOutputFile(outputFilename, &errorMessage));
|
||||||
|
if (!*outputFile) {
|
||||||
|
llvm::errs() << errorMessage << "\n";
|
||||||
|
return failure();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Process the input.
|
||||||
|
if (failed(processInput(context, ts, std::move(input), outputFile)))
|
||||||
|
return failure();
|
||||||
|
|
||||||
|
// If the result succeeded and we're emitting a file, close it.
|
||||||
|
if (outputFile.has_value())
|
||||||
|
(*outputFile)->keep();
|
||||||
|
|
||||||
|
return success();
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Main driver for ibistool command. This sets up LLVM and MLIR, and parses
|
||||||
|
/// command line options before passing off to 'executeIbistool'. This is set
|
||||||
|
/// up so we can `exit(0)` at the end of the program to avoid teardown of the
|
||||||
|
/// MLIRContext and modules inside of it (reducing compile time).
|
||||||
|
int main(int argc, char **argv) {
|
||||||
|
InitLLVM y(argc, argv);
|
||||||
|
|
||||||
|
// Set the bug report message to indicate users should file issues on
|
||||||
|
// llvm/circt and not llvm/llvm-project.
|
||||||
|
setBugReportMsg(circtBugReportMsg);
|
||||||
|
|
||||||
|
// Hide default LLVM options, other than for this tool.
|
||||||
|
// MLIR options are added below.
|
||||||
|
cl::HideUnrelatedOptions(mainCategory);
|
||||||
|
|
||||||
|
// Register any pass manager command line options.
|
||||||
|
registerMLIRContextCLOptions();
|
||||||
|
registerPassManagerCLOptions();
|
||||||
|
registerDefaultTimingManagerCLOptions();
|
||||||
|
registerAsmPrinterCLOptions();
|
||||||
|
|
||||||
|
// Parse pass names in main to ensure static initialization completed.
|
||||||
|
cl::ParseCommandLineOptions(argc, argv, "CIRCT Ibis tool\n");
|
||||||
|
|
||||||
|
DialectRegistry registry;
|
||||||
|
// Register MLIR dialects.
|
||||||
|
registry.insert<mlir::memref::MemRefDialect>();
|
||||||
|
registry.insert<mlir::func::FuncDialect>();
|
||||||
|
registry.insert<mlir::arith::ArithDialect>();
|
||||||
|
registry.insert<mlir::cf::ControlFlowDialect>();
|
||||||
|
registry.insert<mlir::scf::SCFDialect>();
|
||||||
|
|
||||||
|
// Register MLIR passes.
|
||||||
|
mlir::registerCSEPass();
|
||||||
|
mlir::registerSCCPPass();
|
||||||
|
mlir::registerInlinerPass();
|
||||||
|
mlir::registerCanonicalizerPass();
|
||||||
|
|
||||||
|
// Register CIRCT dialects.
|
||||||
|
registry.insert<hw::HWDialect, comb::CombDialect, seq::SeqDialect,
|
||||||
|
sv::SVDialect, handshake::HandshakeDialect, ibis::IbisDialect,
|
||||||
|
dc::DCDialect, esi::ESIDialect, pipeline::PipelineDialect>();
|
||||||
|
|
||||||
|
// Do the guts of the ibistool process.
|
||||||
|
MLIRContext context(registry);
|
||||||
|
auto result = executeIbistool(context);
|
||||||
|
|
||||||
|
// Use "exit" instead of return'ing to signal completion. This avoids
|
||||||
|
// invoking the MLIRContext destructor, which spends a bunch of time
|
||||||
|
// deallocating memory etc which process exit will do for us.
|
||||||
|
exit(failed(result));
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue