From 68b79fc35fcc2d68abc8a0b830c0f5a303af3f04 Mon Sep 17 00:00:00 2001
From: Nandor Licker <n@ndor.email>
Date: Tue, 5 Sep 2023 03:12:34 -0700
Subject: [PATCH] [NFC][Seq] Add folders to clock conversions

---
 include/circt/Dialect/Seq/SeqOps.td | 12 +++++++-----
 lib/Dialect/Seq/SeqOps.cpp          | 12 ++++++++++++
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/include/circt/Dialect/Seq/SeqOps.td b/include/circt/Dialect/Seq/SeqOps.td
index 8e0c24d3ff..e6781bf75f 100644
--- a/include/circt/Dialect/Seq/SeqOps.td
+++ b/include/circt/Dialect/Seq/SeqOps.td
@@ -47,7 +47,7 @@ def CompRegOp : SeqOp<"compreg",
       return build($_builder, $_state, input.getType(), input, clk, nameAttr,
                    Value(), Value(), hw::InnerSymAttr::get(nameAttr));
     }]>,
-    /// Create a register with a reset, with an inner_sym matching the 
+    /// Create a register with a reset, with an inner_sym matching the
     /// register's name.
     OpBuilder<(ins "Value":$input, "Value":$clk, "Value":$reset,
                    "Value":$rstValue, "StringRef":$name), [{
@@ -246,10 +246,10 @@ class HLMemTypeIndexingConstraint<string hlmemvalue, string addresses>
 def ReadPortOp : SeqOp<"read", [
     DeclareOpInterfaceMethods<OpAsmOpInterface, ["getAsmResultNames"]>,
     HLMemTypeIndexingConstraint<"memory", "addresses">,
-    AttrSizedOperandSegments     
+    AttrSizedOperandSegments
   ]> {
   let summary = "Structural read access to a seq.hlmem, with an optional read enable signal.";
-  let arguments = (ins 
+  let arguments = (ins
     HLMemType:$memory,
     Variadic<HWIntegerType>:$addresses,
     Optional<I1>:$rdEn,
@@ -331,8 +331,8 @@ def ClockGateOp : SeqOp<"clock_gate", [
 def ClockMuxOp : SeqOp<"clock_mux", [Pure]> {
   let summary = "Safely selects a clock based on a condition";
   let description = [{
-    The `seq.clock_mux` op selects a clock from two options. If `cond` is 
-    true, the first clock operand is selected to drive downstream logic. 
+    The `seq.clock_mux` op selects a clock from two options. If `cond` is
+    true, the first clock operand is selected to drive downstream logic.
     Otherwise, the second clock is used.
 
     ```
@@ -544,6 +544,7 @@ def ToClockOp : SeqOp<"to_clock", [Pure]> {
 
   let assemblyFormat = "$input attr-dict";
 
+  let hasFolder = 1;
   let hasCanonicalizeMethod = 1;
 }
 
@@ -555,5 +556,6 @@ def FromClockOp : SeqOp<"from_clock", [Pure]> {
 
   let assemblyFormat = "$input attr-dict";
 
+  let hasFolder = 1;
   let hasCanonicalizeMethod = 1;
 }
diff --git a/lib/Dialect/Seq/SeqOps.cpp b/lib/Dialect/Seq/SeqOps.cpp
index eb9855c1ec..2a31b19563 100644
--- a/lib/Dialect/Seq/SeqOps.cpp
+++ b/lib/Dialect/Seq/SeqOps.cpp
@@ -896,6 +896,12 @@ LogicalResult ToClockOp::canonicalize(ToClockOp op, PatternRewriter &rewriter) {
   return failure();
 }
 
+OpFoldResult ToClockOp::fold(FoldAdaptor adaptor) {
+  if (auto fromClock = getInput().getDefiningOp<FromClockOp>())
+    return fromClock.getInput();
+  return {};
+}
+
 LogicalResult FromClockOp::canonicalize(FromClockOp op,
                                         PatternRewriter &rewriter) {
   if (auto toClock = op.getInput().getDefiningOp<ToClockOp>()) {
@@ -905,6 +911,12 @@ LogicalResult FromClockOp::canonicalize(FromClockOp op,
   return failure();
 }
 
+OpFoldResult FromClockOp::fold(FoldAdaptor adaptor) {
+  if (auto toClock = getInput().getDefiningOp<ToClockOp>())
+    return toClock.getInput();
+  return {};
+}
+
 //===----------------------------------------------------------------------===//
 // TableGen generated logic.
 //===----------------------------------------------------------------------===//