mirror of https://github.com/llvm/circt.git
Removed intermediate wire between instances and output operations (#1351)
* Implemented tiny optimisation where it removes intermediate wires between instances and outputs * Removed unnecessary import for iostream * Added some tests * Added some more tests * Fixed tests * Implemented most of what Lattner suggested * Fixed the bug with outputs being null * Did nit picky stuff
This commit is contained in:
Laura Gallo
GitHub
parent
06c5ae9e98
commit
5d22741472
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@ -1,6 +1,9 @@
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/build*
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/docker_build
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tags
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.vscode
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compile_commands.json
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.cache/
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#*
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*~
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.DS_Store
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@ -1916,13 +1916,21 @@ LogicalResult StmtEmitter::visitStmt(OutputOp op) {
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for (ModulePortInfo port : parent.getPorts()) {
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if (!port.isOutput())
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continue;
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auto operand = op.getOperand(operandIndex);
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if (operand.hasOneUse() &&
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dyn_cast_or_null<InstanceOp>(operand.getDefiningOp())) {
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++operandIndex;
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continue;
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}
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ops.clear();
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ops.insert(op);
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indent();
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if (isZeroBitType(port.type))
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os << "// Zero width: ";
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os << "assign " << names.getOutputName(port.argNum) << " = ";
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emitExpression(op.getOperand(operandIndex), ops);
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emitExpression(operand, ops);
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os << ';';
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emitLocationInfoAndNewLine(ops);
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++operandIndex;
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@ -2417,10 +2425,23 @@ LogicalResult StmtEmitter::visitStmt(InstanceOp op) {
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// Emit the value as an expression.
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ops.clear();
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// output ports were lowered to wire
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if (elt.isOutput())
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// Output ports that are not connected to single use output ports were
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// lowered to wire.
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OutputOp output;
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if (!elt.isOutput()) {
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emitExpression(portVal, ops);
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} else if (portVal.hasOneUse() &&
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(output = dyn_cast_or_null<OutputOp>(
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portVal.getUses().begin()->getOwner()))) {
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auto module = output->getParentOfType<HWModuleOp>();
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auto name = getModuleResultNameAttr(
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module, portVal.getUses().begin()->getOperandNumber());
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os << name.getValue().str();
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} else {
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portVal = getWireForValue(portVal);
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emitExpression(portVal, ops);
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emitExpression(portVal, ops);
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}
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os << ')';
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}
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if (!isFirst) {
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@ -2688,22 +2709,30 @@ static void lowerInstanceResults(InstanceOp op) {
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if (onlyUseIsConnect(result))
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continue;
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nameTmp.resize(namePrefixSize);
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if (port.name)
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nameTmp += port.name.getValue().str();
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else
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nameTmp += std::to_string(nextResultNo - 1);
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auto newWire = builder.create<WireOp>(result.getType(), nameTmp);
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while (!result.use_empty()) {
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auto newWireRead = builder.create<ReadInOutOp>(newWire);
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bool isOneUseOutput = false;
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if (result.hasOneUse()) {
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OpOperand &use = *result.getUses().begin();
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use.set(newWireRead);
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newWireRead->moveBefore(use.getOwner());
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isOneUseOutput = dyn_cast_or_null<OutputOp>(use.getOwner()) != nullptr;
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}
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auto connect = builder.create<ConnectOp>(newWire, result);
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connect->moveAfter(op);
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if (!isOneUseOutput) {
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nameTmp.resize(namePrefixSize);
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if (port.name)
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nameTmp += port.name.getValue().str();
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else
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nameTmp += std::to_string(nextResultNo - 1);
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auto newWire = builder.create<WireOp>(result.getType(), nameTmp);
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while (!result.use_empty()) {
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auto newWireRead = builder.create<ReadInOutOp>(newWire);
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OpOperand &use = *result.getUses().begin();
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use.set(newWireRead);
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newWireRead->moveBefore(use.getOwner());
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}
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auto connect = builder.create<ConnectOp>(newWire, result);
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connect->moveAfter(op);
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}
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}
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}
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@ -205,50 +205,44 @@ hw.module @AB(%w: i1, %x: i1, %i2: i2, %i3: i0) -> (%y: i1, %z: i1, %p: i1, %p2:
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hw.output %y, %x, %p, %p2 : i1, i1, i1, i1
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}
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// CHECK-LABEL: module AB(
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// CHECK-NEXT: input w, x,
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// CHECK-NEXT: input [1:0] i2,
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// CHECK-NEXT: // input /*Zero Width*/ i3,
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// CHECK-NEXT: output y, z, p, p2);
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// CHECK-EMPTY:
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// CHECK-LABEL: module AB(
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// CHECK-NEXT: input w, x,
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// CHECK-NEXT: input [1:0] i2,
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// CHECK-NEXT: // input /*Zero Width*/ i3,
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// CHECK-NEXT: output y, z, p, p2);
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// CHECK-EMPTY:
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// CHECK-NEXT: wire b1_b;
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// CHECK-NEXT: wire a1_f;
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// CHECK-EMPTY:
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// CHECK-NEXT: AAA a1 (
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// CHECK-NEXT: .d (w),
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// CHECK-NEXT: .e (b1_b),
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// CHECK-NEXT: .f (a1_f)
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// CHECK-NEXT: );
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// CHECK-NEXT: B b1 (
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// CHECK-NEXT: .a (a1_f),
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// CHECK-NEXT: .b (b1_b),
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// CHECK-NEXT: .c (y)
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// CHECK-NEXT: );
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// CHECK-NEXT: FooModule #(
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// CHECK-NEXT: .DEFAULT(64'd14000240888948784983),
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// CHECK-NEXT: .DEPTH(3.242000e+01),
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// CHECK-NEXT: .FORMAT("xyz_timeout=%d\n"),
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// CHECK-NEXT: .WIDTH(8'd32)
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// CHECK-NEXT: ) paramd (
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// CHECK-NEXT: .a (w),
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// CHECK-NEXT: //.b (i3),
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// CHECK-NEXT: .out (p)
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// CHECK-NEXT: );
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// CHECK-NEXT: FooModule #(
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// CHECK-NEXT: .DEFAULT(64'd1)
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// CHECK-NEXT: ) paramd2 (
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// CHECK-NEXT: .a (i2),
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// CHECK-NEXT: .out (p2)
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// CHECK-NEXT: );
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// CHECK-NEXT: assign z = x;
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// CHECK-NEXT: endmodule
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// CHECK-NEXT: wire paramd2_out;
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// CHECK-NEXT: wire paramd_out;
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// CHECK-NEXT: wire b1_b;
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// CHECK-NEXT: wire b1_c;
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// CHECK-NEXT: wire a1_f;
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// CHECK-EMPTY:
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// CHECK-NEXT: A a1 (
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// CHECK-NEXT: .d (w),
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// CHECK-NEXT: .e (b1_b),
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// CHECK-NEXT: .f (a1_f)
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// CHECK-NEXT: )
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// CHECK-NEXT: B b1 (
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// CHECK-NEXT: .a (a1_f),
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// CHECK-NEXT: .b (b1_b),
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// CHECK-NEXT: .c (b1_c)
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// CHECK-NEXT: )
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// CHECK-NEXT: FooModule #(
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// CHECK-NEXT: .DEFAULT(64'd14000240888948784983),
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// CHECK-NEXT: .DEPTH(3.242000e+01),
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// CHECK-NEXT: .FORMAT("xyz_timeout=%d\n"),
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// CHECK-NEXT: .WIDTH(8'd32)
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// CHECK-NEXT: ) paramd (
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// CHECK-NEXT: .a (w),
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// CHECK-NEXT: .b (i3),
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// CHECK-NEXT: .out (paramd_out)
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// CHECK-NEXT: );
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// CHECK-NEXT: FooModule #(
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// CHECK-NEXT: .DEFAULT(64'd1)
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// CHECK-NEXT: ) paramd2 (
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// CHECK-NEXT: .a (i2),
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// CHECK-NEXT: .out (paramd2_out)
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// CHECK-NEXT: );
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// CHECK-NEXT: assign y = b1_c;
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// CHECK-NEXT: assign z = x;
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// CHECK-NEXT: assign p = paramd_out;
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// CHECK-NEXT: assign p2 = paramd2_out;
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// CHECK-NEXT: endmodule
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hw.module @shl(%a: i1) -> (%b: i1) {
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@ -447,21 +441,19 @@ hw.module @TestZero(%a: i4, %zeroBit: i0, %arrZero: !hw.array<3xi0>)
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hw.module @TestZeroInstance(%aa: i4, %azeroBit: i0, %aarrZero: !hw.array<3xi0>)
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-> (%r0: i4, %rZero: i0, %arrZero_0: !hw.array<3xi0>) {
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// CHECK: TestZero iii ( // {{.*}}hw-dialect.mlir:{{.*}}:19
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// CHECK: .a (aa),
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// CHECK: //.zeroBit (azeroBit),
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// CHECK: //.arrZero (aarrZero),
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// CHECK: .r0 (iii_r0)
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// CHECK: //.rZero (iii_rZero)
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// CHECK: //.arrZero_0 (iii_arrZero_0)
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// CHECK: );
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// CHECK: TestZero iii (
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// CHECK-NEXT: .a (aa),
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// CHECK-NEXT: //.zeroBit (azeroBit),
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// CHECK-NEXT: //.arrZero (aarrZero),
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// CHECK-NEXT: .r0 (r0)
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// CHECK-NEXT: //.rZero (rZero)
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// CHECK-NEXT: //.arrZero_0 (arrZero_0)
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// CHECK-NEXT: );
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// CHECK-NEXT: endmodule
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%o1, %o2, %o3 = hw.instance "iii" @TestZero(%aa, %azeroBit, %aarrZero)
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: (i4, i0, !hw.array<3xi0>) -> (i4, i0, !hw.array<3xi0>)
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// CHECK: assign r0 = iii_r0;
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// CHECK: // Zero width: assign rZero = iii_rZero;
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// CHECK: // Zero width: assign arrZero_0 = iii_arrZero_0;
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hw.output %o1, %o2, %o3 : i4, i0, !hw.array<3xi0>
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}
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@ -638,21 +630,83 @@ hw.module.extern @ExternDestMod(%a: i1, %b: i2) -> (%c: i3, %d: i4)
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hw.module @InternalDestMod(%a: i1, %b: i3) {}
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// CHECK-LABEL module ABC
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hw.module @ABC(%a: i1, %b: i2) -> (%c: i4) {
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// CHECK: wire [2:0] whatever_c;
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// CHECK: wire [3:0] whatever_d;
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%0,%1 = hw.instance "whatever" sym @a1 @ExternDestMod(%a, %b) {doNotPrint=1}: (i1, i2) -> (i3, i4)
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// CHECK: // ExternDestMod whatever (
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// CHECK-NEXT: // .a (a),
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// CHECK-NEXT: // .b (b),
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// CHECK-NEXT: // .c (whatever_c),
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// CHECK-NEXT: // .d (whatever_d)
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// CHECK-NEXT: // );
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hw.instance "yo" sym @b1 @InternalDestMod(%a, %0) {doNotPrint=1} : (i1, i3) -> ()
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// CHECK-NEXT: // InternalDestMod yo (
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// CHECK-NEXT: // .a (a),
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// CHECK-NEXT: // .b (whatever_c)
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// CHECK-NEXT: // );
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hw.output %1 : i4
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// CHECK-NEXT: assign c = whatever_d;
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// CHECK-NEXT: endmodule
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}
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// CHECK: wire [2:0] whatever_c;
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// CHECK-EMPTY:
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// CHECK-NEXT: // ExternDestMod whatever (
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// CHECK-NEXT: // .a (a),
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// CHECK-NEXT: // .b (b),
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// CHECK-NEXT: // .c (whatever_c),
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// CHECK-NEXT: // .d (c)
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// CHECK-NEXT: // );
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// CHECK-NEXT: // InternalDestMod yo (
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// CHECK-NEXT: // .a (a),
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// CHECK-NEXT: // .b (whatever_c)
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// CHECK-NEXT: // );
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// CHECK-NEXT: endmodule
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hw.module.extern @Uwu() -> (%uwu_output : i32)
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hw.module.extern @Owo(%owo_in : i32) -> ()
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// CHECK-LABEL: module Nya(
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hw.module @Nya() -> (%nya_output : i32) {
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%0 = hw.instance "uwu" @Uwu() : () -> (i32)
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// CHECK: wire [31:0] uwu_uwu_output;
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// CHECK-EMPTY:
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// CHECK: Uwu uwu (
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// CHECK: .uwu_output (uwu_uwu_output)
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// CHECK: );
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hw.instance "owo" @Owo(%0) : (i32) -> ()
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// CHECK: Owo owo (
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// CHECK: .owo_in (uwu_uwu_output)
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// CHECK: );
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hw.output %0 : i32
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// CHECK: assign nya_output = uwu_uwu_output;
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// CHECK: endmodule
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}
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// CHECK-LABEL: module Nya2(
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hw.module @Nya2() -> (%nya2_output : i32) {
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%0 = hw.instance "uwu" @Uwu() : () -> (i32)
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// CHECK: Uwu uwu (
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// CHECK: .uwu_output (nya2_output)
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// CHECK: );
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hw.output %0 : i32
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// CHECK: endmodule
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}
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hw.module.extern @Ni() -> (%ni_output : i0)
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hw.module.extern @San(%san_input : i0) -> ()
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// CHECK-LABEL: module Ichi(
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hw.module @Ichi() -> (%Ichi_output : i0) {
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%0 = hw.instance "ni" @Ni() : () -> (i0)
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// CHECK: Ni ni (
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// CHECK: //.ni_output (Ichi_output));
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hw.output %0 : i0
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// CHECK: endmodule
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}
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// CHECK-LABEL: module Chi(
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hw.module @Chi() -> (%Chi_output : i0) {
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%0 = hw.instance "ni" @Ni() : () -> (i0)
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// CHECK: Ni ni (
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// CHECK: //.ni_output (ni_ni_output));
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hw.instance "san" @San(%0) : (i0) -> ()
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// CHECK: San san (
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// CHECK: //.san_input (ni_ni_output));
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// CHECK: // Zero width: assign Chi_output = ni_ni_output;
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hw.output %0 : i0
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// CHECK: endmodule
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}
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