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[ExportVerilog] Merging `MLIRModuleEmitter` and `ModuleEmitter`

This commit is contained in:
John Demme 2021-02-20 16:37:23 -08:00
parent 49a3f99355
commit 5ad5992b67
1 changed files with 15 additions and 25 deletions
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40
lib/Translation/ExportVerilog/ExportVerilog.cpp
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@ -309,6 +309,7 @@ public:
explicit ModuleEmitter(VerilogEmitterState &state)
: VerilogEmitterBase(state) {}
void emitMLIRModule(ModuleOp module);
void emitRTLModule(RTLModuleOp module);
void emitRTLExternModule(RTLModuleExternOp module);
void emitExpression(Value exp, SmallPtrSet<Operation *, 8> &emittedExprs,
@ -2067,6 +2068,19 @@ void ModuleEmitter::emitOperation(Operation *op) {
indent() << "unknown MLIR operation " << op->getName().getStringRef() << "\n";
}
void ModuleEmitter::emitMLIRModule(ModuleOp module) {
for (auto &op : *module.getBody()) {
if (auto module = dyn_cast<RTLModuleOp>(op))
ModuleEmitter(state).emitRTLModule(module);
else if (auto module = dyn_cast<RTLModuleExternOp>(op))
ModuleEmitter(state).emitRTLExternModule(module);
else if (isa<InterfaceOp>(op) || isa<VerbatimOp>(op) || isa<IfDefOp>(op))
ModuleEmitter(state).emitOperation(&op);
else if (!isa<ModuleTerminatorOp>(op))
op.emitError("unknown operation");
}
}
void ModuleEmitter::emitRTLExternModule(RTLModuleExternOp module) {
os << "// external module " << module.getName() << "\n\n";
}
@ -2205,33 +2219,9 @@ void ModuleEmitter::emitRTLModule(RTLModuleOp module) {
// MLIRModuleEmitter
//===----------------------------------------------------------------------===//
namespace {
class MLIRModuleEmitter : public VerilogEmitterBase {
public:
explicit MLIRModuleEmitter(VerilogEmitterState &state)
: VerilogEmitterBase(state) {}
void emit(ModuleOp module);
};
} // end anonymous namespace
void MLIRModuleEmitter::emit(ModuleOp module) {
for (auto &op : *module.getBody()) {
if (auto module = dyn_cast<RTLModuleOp>(op))
ModuleEmitter(state).emitRTLModule(module);
else if (auto module = dyn_cast<RTLModuleExternOp>(op))
ModuleEmitter(state).emitRTLExternModule(module);
else if (isa<InterfaceOp>(op) || isa<VerbatimOp>(op) || isa<IfDefOp>(op))
ModuleEmitter(state).emitOperation(&op);
else if (!isa<ModuleTerminatorOp>(op))
op.emitError("unknown operation");
}
}
LogicalResult circt::exportVerilog(ModuleOp module, llvm::raw_ostream &os) {
VerilogEmitterState state(os);
MLIRModuleEmitter(state).emit(module);
ModuleEmitter(state).emitMLIRModule(module);
return failure(state.encounteredError);
}