mirror of https://github.com/llvm/circt.git
[FSMToSV] Add FSM to SV conversion pass (#3483)
This commit introduces an FSM to SV lowering pass, as well as some small modifications to the FSM dialect to facilitate the conversion. This initial version of the pass does not support transition action regions and variables.
The lowering style is fairly straight forward; two processes are emitted, one `always_ff` for state register inference, one `always_comb` for next-state calculation and output assignments.
e.g.:
```mlir
fsm.machine @top(%a0: i1, %arg1: i1) -> (i8, i8) attributes {initialState = "A", argNames = ["a0", "a1"], resNames = ["r0", "r1"]} {
%c_42 = hw.constant 42 : i8
fsm.state @A output {
%c_0 = hw.constant 0 : i8
fsm.output %c_0, %c_42 : i8, i8
} transitions {
fsm.transition @B
}
fsm.state @B output {
%c_1 = hw.constant 1 : i8
fsm.output %c_1, %c_42 : i8, i8
} transitions {
fsm.transition @A guard {
%g = comb.and %a0, %arg1 : i1
fsm.return %g
}
}
}
```
emits as
```sv
typedef enum {A, B} top_state_t;
module top(
input a0,
a1,
clk,
rst,
output [7:0] r0,
r1);
reg [7:0] output_1;
reg [7:0] output_0;
top_state_t next_state;
wire top_state_t to_A;
wire top_state_t to_B;
top_state_t state_reg;
assign to_A = A;
assign to_B = B;
always_ff @(posedge clk) begin
if (rst)
state_reg <= to_A;
else
state_reg <= next_state;
end
always_comb begin
case (state_reg)
A: begin
next_state = to_B;
output_0 = 8'h0;
output_1 = 8'h2A;
end
B: begin
next_state = a0 & a1 ? to_A : to_B;
output_0 = 8'h1;
output_1 = 8'h2A;
end
endcase
end
assign r0 = output_0;
assign r1 = output_1;
endmodule
```
This commit is contained in:
Morten Borup Petersen
GitHub
parent
f1ed562e0e
commit
56a260a1d4
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@ -24,7 +24,7 @@ with the following features:
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internal variables of an FSM, allowing convenient analysis and transformation.
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2. Provide a target-agnostic representation of FSM, allowing the state machine
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to be instantiated and attached to other dialects from different domains.
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3. By cooperating with two conversion passes, FSMToHW and FSMToStandard, allow
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3. By cooperating with two conversion passes, FSMToSV and FSMToStandard, allow
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to lower the FSM abstraction into HW+Comb+SV (Hardware) and Standard+SCF+MemRef
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(Software) dialects for the purposes of simulation, code generation, etc.
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@ -0,0 +1,22 @@
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//===- FSMToSV.h - FSM to SV conversions ------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_CONVERSION_FSMTOSV_FSMTOSV_H
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#define CIRCT_CONVERSION_FSMTOSV_FSMTOSV_H
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#include <memory>
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namespace mlir {
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class Pass;
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} // namespace mlir
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namespace circt {
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std::unique_ptr<mlir::Pass> createConvertFSMToSVPass();
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} // namespace circt
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#endif // CIRCT_CONVERSION_FSMTOSV_FSMTOSV_H
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@ -17,6 +17,7 @@
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#include "circt/Conversion/CalyxToHW.h"
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#include "circt/Conversion/ExportVerilog.h"
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#include "circt/Conversion/FIRRTLToHW.h"
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#include "circt/Conversion/FSMToSV.h"
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#include "circt/Conversion/HWToLLHD.h"
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#include "circt/Conversion/HandshakeToFIRRTL.h"
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#include "circt/Conversion/HandshakeToHW.h"
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@ -147,6 +147,17 @@ def CalyxToHW : Pass<"lower-calyx-to-hw", "mlir::ModuleOp"> {
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"seq::SeqDialect", "sv::SVDialect"];
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}
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//===----------------------------------------------------------------------===//
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// FSMToSV
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//===----------------------------------------------------------------------===//
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def ConvertFSMToSV : Pass<"convert-fsm-to-sv", "mlir::ModuleOp"> {
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let summary = "Convert FSM to HW";
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let constructor = "circt::createConvertFSMToSVPass()";
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let dependentDialects = ["circt::hw::HWDialect", "circt::comb::CombDialect",
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"circt::seq::SeqDialect", "circt::sv::SVDialect"];
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}
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//===----------------------------------------------------------------------===//
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// FIRRTLToHW
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//===----------------------------------------------------------------------===//
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@ -25,7 +25,9 @@ def MachineOp : FSMOp<"machine", [FunctionOpInterface,
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}];
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let arguments = (ins StrAttr:$sym_name, StrAttr:$initialState,
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TypeAttrOf<FunctionType>:$function_type);
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TypeAttrOf<FunctionType>:$function_type,
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OptionalAttr<StrArrayAttr>:$argNames,
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OptionalAttr<StrArrayAttr>:$resNames);
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let regions = (region SizedRegion<1>:$body);
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let builders = [
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@ -47,6 +49,12 @@ def MachineOp : FSMOp<"machine", [FunctionOpInterface,
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return getFunctionTypeAttr().getValue().cast<FunctionType>();
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}
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/// Returns the number of states in this machhine.
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size_t getNumStates() {
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auto stateOps = getBody().getOps<fsm::StateOp>();
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return std::distance(stateOps.begin(), stateOps.end());
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}
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/// Returns the argument types of this function.
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ArrayRef<Type> getArgumentTypes() { return getFunctionType().getInputs(); }
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@ -112,7 +120,7 @@ def TriggerOp : FSMOp<"trigger", []> {
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let hasVerifier = 1;
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}
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def HWInstanceOp : FSMOp<"hw_instance", [Symbol, AttrSizedOperandSegments]> {
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def HWInstanceOp : FSMOp<"hw_instance", [Symbol]> {
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let summary = "Create a hardware-style instance of a state machine";
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let description = [{
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`fsm.hw_instance` represents a hardware-style instance of a state machine,
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@ -122,14 +130,12 @@ def HWInstanceOp : FSMOp<"hw_instance", [Symbol, AttrSizedOperandSegments]> {
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}];
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let arguments = (ins StrAttr:$sym_name, FlatSymbolRefAttr:$machine,
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Variadic<AnyType>:$inputs, Optional<AnyType>:$clock,
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Optional<AnyType>:$reset);
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Variadic<AnyType>:$inputs, I1:$clock, I1:$reset);
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let results = (outs Variadic<AnyType>:$outputs);
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let assemblyFormat = [{
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$sym_name $machine attr-dict `(` $inputs `)` `:`
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functional-type($inputs, $outputs) (`,` `clock` $clock^ `:` qualified(type($clock)))?
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(`,` `reset` $reset^ `:` qualified(type($reset)))?
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$sym_name $machine attr-dict `(` $inputs `)`
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`,` `clock` $clock `,` `reset` $reset `:` functional-type($inputs, $outputs)
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}];
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let extraClassDeclaration = [{
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@ -0,0 +1,53 @@
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#include "Vtop.h"
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#include "verilated.h"
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#include <iostream>
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int main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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auto *tb = new Vtop;
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// Post-reset start time.
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int t0 = 2;
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for (int i = 0; i < 10; i++) {
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if (i > t0)
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std::cout << "out: " << char('A' + tb->out0) << std::endl;
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// Rising edge
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tb->clk = 1;
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tb->eval();
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// Testbench
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tb->rst = i < t0;
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// t0: Starts in A,
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// t0+1: Default transition to B
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if (i == t0 + 2) {
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// B -> C
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tb->in0 = 1;
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tb->in1 = 1;
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}
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if (i == t0 + 3) {
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// C -> B
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tb->in0 = 0;
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tb->in1 = 0;
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}
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if (i == t0 + 4 || i == t0 + 5) {
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// B -> C, C-> A
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tb->in0 = 1;
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tb->in1 = 1;
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}
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// t0+6: Default transition to B
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// Falling edge
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tb->clk = 0;
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tb->eval();
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}
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exit(EXIT_SUCCESS);
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}
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@ -0,0 +1 @@
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config.excludes.add('driver.cpp')
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@ -0,0 +1,41 @@
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// REQUIRES: verilator
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// RUN: circt-opt %s --convert-fsm-to-sv --canonicalize --lower-seq-to-sv --export-verilog -o %t2.mlir > %t1.sv
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// RUN: circt-rtl-sim.py %t1.sv %S/driver.cpp | FileCheck %s
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// CHECK: out: A
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// CHECK: out: B
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// CHECK: out: B
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// CHECK: out: C
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// CHECK: out: B
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// CHECK: out: C
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// CHECK: out: A
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fsm.machine @top(%arg0: i1, %arg1: i1) -> (i8) attributes {initialState = "A"} {
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fsm.state @A output {
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%c_0 = hw.constant 0 : i8
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fsm.output %c_0 : i8
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} transitions {
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fsm.transition @B
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}
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fsm.state @B output {
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%c_1 = hw.constant 1 : i8
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fsm.output %c_1 : i8
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} transitions {
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fsm.transition @C guard {
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%g = comb.and %arg0, %arg1 : i1
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fsm.return %g
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}
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}
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fsm.state @C output {
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%c_2 = hw.constant 2 : i8
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fsm.output %c_2 : i8
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} transitions {
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fsm.transition @A guard {
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%g = comb.and %arg0, %arg1 : i1
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fsm.return %g
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}
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fsm.transition @B
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}
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}
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@ -11,3 +11,4 @@ add_subdirectory(SCFToCalyx)
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add_subdirectory(StaticLogicToCalyx)
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add_subdirectory(StandardToHandshake)
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add_subdirectory(StandardToStaticLogic)
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add_subdirectory(FSMToSV)
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@ -0,0 +1,18 @@
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add_circt_conversion_library(CIRCTFSMToSV
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FSMToSV.cpp
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DEPENDS
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CIRCTConversionPassIncGen
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LINK_COMPONENTS
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Core
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LINK_LIBS PUBLIC
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CIRCTComb
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CIRCTHW
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CIRCTFSM
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CIRCTSeq
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CIRCTSV
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CIRCTSupport
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MLIRTransforms
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)
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@ -0,0 +1,565 @@
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//===- FSMToSV.cpp - Convert FSM to HW and SV Dialect ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Conversion/FSMToSV.h"
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#include "../PassDetail.h"
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#include "circt/Dialect/Comb/CombOps.h"
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#include "circt/Dialect/FSM/FSMOps.h"
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/SV/SVOps.h"
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#include "circt/Dialect/Seq/SeqOps.h"
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#include "circt/Support/BackedgeBuilder.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include <memory>
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using namespace mlir;
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using namespace circt;
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using namespace fsm;
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/// Get the port info of a FSM machine. Clock and reset port are also added.
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namespace {
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struct ClkRstIdxs {
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size_t clockIdx;
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size_t resetIdx;
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};
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} // namespace
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static ClkRstIdxs getMachinePortInfo(SmallVectorImpl<hw::PortInfo> &ports,
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MachineOp machine, OpBuilder &b) {
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// Get the port info of the machine inputs and outputs.
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machine.getHWPortInfo(ports);
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ClkRstIdxs specialPorts;
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// Add clock port.
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hw::PortInfo clock;
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clock.name = b.getStringAttr("clk");
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clock.direction = hw::PortDirection::INPUT;
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clock.type = b.getI1Type();
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clock.argNum = machine.getNumArguments();
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ports.push_back(clock);
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specialPorts.clockIdx = clock.argNum;
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// Add reset port.
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hw::PortInfo reset;
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reset.name = b.getStringAttr("rst");
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reset.direction = hw::PortDirection::INPUT;
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reset.type = b.getI1Type();
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reset.argNum = machine.getNumArguments() + 1;
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ports.push_back(reset);
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specialPorts.resetIdx = reset.argNum;
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return specialPorts;
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}
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namespace {
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class StateEncoding {
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// An class for handling state encoding. The class is designed to
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// abstract away how states are selected in case patterns, referred to as
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// values, and used as selection signals for muxes.
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public:
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StateEncoding(OpBuilder &b, MachineOp machine, hw::HWModuleOp hwModule);
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// Get the encoded value for a state.
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Value encode(StateOp state);
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// Get the state corresponding to an encoded value.
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StateOp decode(Value value);
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// Returns the type which encodes the state values.
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Type getStateType() { return stateType; }
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// Returns a case pattern which matches the provided state.
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std::unique_ptr<sv::CasePattern> getCasePattern(StateOp state);
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protected:
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// Creates a constant value in the module for the given encoded state
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// and records the state value in the mappings. An inner symbol is
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// attached to the wire to avoid it being optimized away.
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// The constant can optionally be assigned behind a sv wire - doing so at this
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// point ensures that constants don't end up behind "_GEN#" wires in the
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// module.
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void setEncoding(StateOp state, Value v, bool wire = false);
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// A mapping between a StateOp and its corresponding encoded value.
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SmallDenseMap<StateOp, Value> stateToValue;
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// A mapping between an encoded value and its corresponding StateOp.
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SmallDenseMap<Value, StateOp> valueToState;
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// A mapping between an encoded value and the source value in the IR.
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SmallDenseMap<Value, Value> valueToSrcValue;
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// The enum type for the states.
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Type stateType;
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OpBuilder &b;
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MachineOp machine;
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hw::HWModuleOp hwModule;
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};
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StateEncoding::StateEncoding(OpBuilder &b, MachineOp machine,
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hw::HWModuleOp hwModule)
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: b(b), machine(machine), hwModule(hwModule) {
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Location loc = machine.getLoc();
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llvm::SmallVector<Attribute> stateNames;
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for (auto state : machine.getBody().getOps<StateOp>())
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stateNames.push_back(b.getStringAttr(state.getName()));
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// Create an enum typedef for the states.
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Type rawEnumType =
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hw::EnumType::get(b.getContext(), b.getArrayAttr(stateNames));
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OpBuilder::InsertionGuard guard(b);
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b.setInsertionPoint(hwModule);
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auto typeScope = b.create<hw::TypeScopeOp>(
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loc, b.getStringAttr(hwModule.getName() + "_enum_typedecls"));
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typeScope.getBodyRegion().push_back(new Block());
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b.setInsertionPointToStart(&typeScope.getBodyRegion().front());
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auto typedeclEnumType = b.create<hw::TypedeclOp>(
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loc, b.getStringAttr(hwModule.getName() + "_state_t"),
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TypeAttr::get(rawEnumType), nullptr);
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stateType = hw::TypeAliasType::get(
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SymbolRefAttr::get(typeScope.sym_nameAttr(),
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{FlatSymbolRefAttr::get(typedeclEnumType)}),
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rawEnumType);
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// And create enum values for the states
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b.setInsertionPointToStart(&hwModule.getBody().front());
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for (auto state : machine.getBody().getOps<StateOp>()) {
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auto fieldAttr = hw::EnumFieldAttr::get(
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loc, b.getStringAttr(state.getName()), stateType);
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auto enumConstantOp = b.create<hw::EnumConstantOp>(
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loc, fieldAttr.getType().getValue(), fieldAttr);
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setEncoding(state, enumConstantOp,
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/*wire=*/true);
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}
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}
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// Get the encoded value for a state.
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Value StateEncoding::encode(StateOp state) {
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auto it = stateToValue.find(state);
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assert(it != stateToValue.end() && "state not found");
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return it->second;
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}
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// Get the state corresponding to an encoded value.
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StateOp StateEncoding::decode(Value value) {
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auto it = valueToState.find(value);
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assert(it != valueToState.end() && "encoded state not found");
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return it->second;
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}
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// Returns a case pattern which matches the provided state.
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std::unique_ptr<sv::CasePattern> StateEncoding::getCasePattern(StateOp state) {
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// Get the field attribute for the state - fetch it through the encoding.
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auto fieldAttr =
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cast<hw::EnumConstantOp>(valueToSrcValue[encode(state)].getDefiningOp())
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.fieldAttr();
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return std::make_unique<sv::CaseEnumPattern>(fieldAttr);
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}
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void StateEncoding::setEncoding(StateOp state, Value v, bool wire) {
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assert(stateToValue.find(state) == stateToValue.end() &&
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"state already encoded");
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Value encodedValue;
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if (wire) {
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auto loc = machine.getLoc();
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auto stateType = getStateType();
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auto stateEncodingWire = b.create<sv::WireOp>(
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loc, stateType, b.getStringAttr("to_" + state.getName()),
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/*inner_sym=*/state.getNameAttr());
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b.create<sv::AssignOp>(loc, stateEncodingWire, v);
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encodedValue = b.create<sv::ReadInOutOp>(loc, stateEncodingWire);
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} else
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||||
encodedValue = v;
|
||||
stateToValue[state] = encodedValue;
|
||||
valueToState[encodedValue] = state;
|
||||
valueToSrcValue[encodedValue] = v;
|
||||
}
|
||||
|
||||
class MachineOpConverter {
|
||||
public:
|
||||
MachineOpConverter(OpBuilder &builder, MachineOp machineOp)
|
||||
: machineOp(machineOp), b(builder) {}
|
||||
|
||||
// Converts the machine op to a hardware module.
|
||||
// 1. Creates a HWModuleOp for the machine op, with the same I/O as the FSM +
|
||||
// clk/reset ports.
|
||||
// 2. Creates a state register + encodings for the states visible in the
|
||||
// machine.
|
||||
// 3. Iterates over all states in the machine
|
||||
// 3.1. Moves all `comb` logic into the body of the HW module
|
||||
// 3.2. Records the SSA value(s) associated to the output ports in the state
|
||||
// 3.3. iterates of the transitions of the state
|
||||
// 3.3.1. Moves all `comb` logic in the transition guard/action regions to
|
||||
// the body of the HW module.
|
||||
// 3.3.2. Creates a case pattern for the transition guard
|
||||
// 3.4. Creates a next-state value for the state based on the transition
|
||||
// guards.
|
||||
// 4. Assigns next-state values for the states in a case statement on the
|
||||
// state reg.
|
||||
// 5. Assigns the current-state outputs for the states in a case statement
|
||||
// on the state reg.
|
||||
LogicalResult dispatch();
|
||||
|
||||
private:
|
||||
struct StateConversionResult {
|
||||
// Value of the next state output signal of the converted state.
|
||||
Value nextState;
|
||||
// Value of the output signals of the converted state.
|
||||
llvm::SmallVector<Value> outputs;
|
||||
};
|
||||
|
||||
using StateConversionResults = DenseMap<StateOp, StateConversionResult>;
|
||||
|
||||
// Converts a StateOp within this machine, and returns the value corresponding
|
||||
// to the next-state output of the op.
|
||||
FailureOr<StateConversionResult> convertState(StateOp state);
|
||||
|
||||
// Converts the outgoing transitions of a state and returns the value
|
||||
// corresponding to the next-state output of the op.
|
||||
// Transitions are priority encoded in the order which they appear in the
|
||||
// state transition region.
|
||||
FailureOr<Value> convertTransitions(StateOp currentState,
|
||||
ArrayRef<TransitionOp> transitions);
|
||||
|
||||
// Returns the value that must be assigned to the hw output ports of this
|
||||
// machine.
|
||||
llvm::SmallVector<Value>
|
||||
getOutputAssignments(StateConversionResults &stateConvResults);
|
||||
|
||||
// Moves operations from 'block' into module scope, failing if any op were
|
||||
// deemed illegal. Returns the final op in the block if the op was a
|
||||
// terminator. An optional 'exclude' filer can be provided to dynamically
|
||||
// exclude some ops from being moved.
|
||||
FailureOr<Operation *>
|
||||
moveOps(Block *block,
|
||||
llvm::function_ref<bool(Operation *)> exclude = nullptr);
|
||||
|
||||
// Build a SV case-based combinational mux the values provided in
|
||||
// 'stateToValue' to a retured wire.
|
||||
// 'stateToValue' being a list implies that multiple muxes can be emitted at
|
||||
// once, avoiding bloating the IR with a case statement for every muxed value.
|
||||
// A wire is returned for each srcMap provided.
|
||||
// 'nameF' can be provided to specify the name of the output wire created for
|
||||
// each source map.
|
||||
llvm::SmallVector<Value>
|
||||
buildStateCaseMux(Location loc, Value sel,
|
||||
llvm::ArrayRef<llvm::SmallDenseMap<StateOp, Value>> srcMaps,
|
||||
llvm::function_ref<StringAttr(size_t)> nameF = {});
|
||||
|
||||
// A handle to the state encoder for this machine.
|
||||
std::unique_ptr<StateEncoding> encoding;
|
||||
|
||||
// A deterministic ordering of the states in this machine.
|
||||
llvm::SmallVector<StateOp> orderedStates;
|
||||
|
||||
// A mapping from a state op to its next-state value.
|
||||
llvm::SmallDenseMap<StateOp, Value> nextStateFromState;
|
||||
|
||||
// A handle to the MachineOp being converted.
|
||||
MachineOp machineOp;
|
||||
|
||||
// A handle to the HW ModuleOp being created.
|
||||
hw::HWModuleOp hwModuleOp;
|
||||
|
||||
// A handle to the state register of the machine.
|
||||
seq::CompRegOp stateReg;
|
||||
|
||||
OpBuilder &b;
|
||||
};
|
||||
|
||||
FailureOr<Operation *>
|
||||
MachineOpConverter::moveOps(Block *block,
|
||||
llvm::function_ref<bool(Operation *)> exclude) {
|
||||
for (auto &op : llvm::make_early_inc_range(*block)) {
|
||||
if (!isa<comb::CombDialect, hw::HWDialect, fsm::FSMDialect>(
|
||||
op.getDialect()))
|
||||
return op.emitOpError()
|
||||
<< "is unsupported (op from the "
|
||||
<< op.getDialect()->getNamespace() << " dialect).";
|
||||
|
||||
if (exclude && exclude(&op))
|
||||
continue;
|
||||
|
||||
if (op.hasTrait<OpTrait::IsTerminator>())
|
||||
return &op;
|
||||
|
||||
op.moveBefore(&hwModuleOp.front(), b.getInsertionPoint());
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
llvm::SmallVector<Value> MachineOpConverter::buildStateCaseMux(
|
||||
Location loc, Value sel,
|
||||
llvm::ArrayRef<llvm::SmallDenseMap<StateOp, Value>> srcMaps,
|
||||
llvm::function_ref<StringAttr(size_t)> nameF) {
|
||||
sv::CaseOp caseMux;
|
||||
auto caseMuxCtor = [&]() {
|
||||
caseMux = b.create<sv::CaseOp>(loc, CaseStmtType::CaseStmt, sel,
|
||||
/*numCases=*/machineOp.getNumStates(),
|
||||
[&](size_t caseIdx) {
|
||||
StateOp state = orderedStates[caseIdx];
|
||||
return encoding->getCasePattern(state);
|
||||
});
|
||||
};
|
||||
b.create<sv::AlwaysCombOp>(loc, caseMuxCtor);
|
||||
|
||||
llvm::SmallVector<Value> dsts;
|
||||
// note: cannot use llvm::enumerate, makes the underlying iterator const.
|
||||
size_t idx = 0;
|
||||
for (auto srcMap : srcMaps) {
|
||||
auto valueType = srcMap.begin()->second.getType();
|
||||
StringAttr name;
|
||||
if (nameF)
|
||||
name = nameF(idx);
|
||||
|
||||
auto dst = b.create<sv::RegOp>(loc, valueType, name);
|
||||
OpBuilder::InsertionGuard g(b);
|
||||
for (auto [caseInfo, stateOp] :
|
||||
llvm::zip(caseMux.getCases(), orderedStates)) {
|
||||
b.setInsertionPointToEnd(caseInfo.block);
|
||||
b.create<sv::BPAssignOp>(loc, dst, srcMap[stateOp]);
|
||||
}
|
||||
dsts.push_back(dst);
|
||||
idx++;
|
||||
}
|
||||
return dsts;
|
||||
}
|
||||
|
||||
LogicalResult MachineOpConverter::dispatch() {
|
||||
if (auto varOps = machineOp.front().getOps<VariableOp>(); !varOps.empty())
|
||||
return (*varOps.begin())->emitOpError()
|
||||
<< "FSM variables not yet supported for SV "
|
||||
"lowering.";
|
||||
|
||||
b.setInsertionPoint(machineOp);
|
||||
auto loc = machineOp.getLoc();
|
||||
if (machineOp.getNumStates() < 2)
|
||||
return machineOp.emitOpError() << "expected at least 2 states.";
|
||||
|
||||
// 1) Get the port info of the machine and create a new HW module for it.
|
||||
SmallVector<hw::PortInfo, 16> ports;
|
||||
auto clkRstIdxs = getMachinePortInfo(ports, machineOp, b);
|
||||
hwModuleOp = b.create<hw::HWModuleOp>(loc, machineOp.sym_nameAttr(), ports);
|
||||
b.setInsertionPointToStart(&hwModuleOp.front());
|
||||
|
||||
// Replace all uses of the machine arguments with the arguments of the
|
||||
// new created HW module.
|
||||
for (auto args :
|
||||
llvm::zip(machineOp.getArguments(), hwModuleOp.front().getArguments())) {
|
||||
auto machineArg = std::get<0>(args);
|
||||
auto hwModuleArg = std::get<1>(args);
|
||||
machineArg.replaceAllUsesWith(hwModuleArg);
|
||||
}
|
||||
|
||||
auto clock = hwModuleOp.front().getArgument(clkRstIdxs.clockIdx);
|
||||
auto reset = hwModuleOp.front().getArgument(clkRstIdxs.resetIdx);
|
||||
|
||||
// 2) Build state register.
|
||||
encoding = std::make_unique<StateEncoding>(b, machineOp, hwModuleOp);
|
||||
auto stateType = encoding->getStateType();
|
||||
|
||||
BackedgeBuilder bb(b, loc);
|
||||
auto nextStateBackedge = bb.get(stateType);
|
||||
stateReg = b.create<seq::CompRegOp>(
|
||||
loc, stateType, nextStateBackedge, clock, "state_reg", reset,
|
||||
/*reset value=*/encoding->encode(machineOp.getInitialStateOp()), nullptr);
|
||||
|
||||
// Move any operations at the machine-level scope, excluding state ops, which
|
||||
// are handled separately.
|
||||
if (failed(moveOps(&machineOp.front(),
|
||||
[](Operation *op) { return isa<fsm::StateOp>(op); }))) {
|
||||
bb.abandon();
|
||||
return failure();
|
||||
}
|
||||
|
||||
// 3) Convert states and record their next-state value.
|
||||
StateConversionResults stateConvResults;
|
||||
for (auto state : machineOp.getBody().getOps<StateOp>()) {
|
||||
auto stateConvRes = convertState(state);
|
||||
if (failed(stateConvRes)) {
|
||||
bb.abandon();
|
||||
return failure();
|
||||
}
|
||||
stateConvResults[state] = stateConvRes.getValue();
|
||||
orderedStates.push_back(state);
|
||||
nextStateFromState[state] = stateConvRes.getValue().nextState;
|
||||
}
|
||||
|
||||
// 4/5) Create next-state maps for each output and the next-state signal in a
|
||||
// format suitable for creating a case mux.
|
||||
llvm::SmallVector<llvm::SmallDenseMap<StateOp, Value>, 4> nextStateMaps;
|
||||
nextStateMaps.push_back(nextStateFromState);
|
||||
for (size_t portIndex = 0; portIndex < machineOp.getNumResults();
|
||||
portIndex++) {
|
||||
auto &nsmap = nextStateMaps.emplace_back();
|
||||
for (auto &state : orderedStates)
|
||||
nsmap[state] = stateConvResults[state].outputs[portIndex];
|
||||
}
|
||||
|
||||
// Materialize the case mux. We do this in a single call to have a single
|
||||
// always_comb block.
|
||||
auto stateCaseMuxes = buildStateCaseMux(
|
||||
machineOp.getLoc(), stateReg, nextStateMaps, [&](size_t idx) {
|
||||
if (idx == 0)
|
||||
return b.getStringAttr("next_state");
|
||||
|
||||
return b.getStringAttr("output_" + std::to_string(idx - 1));
|
||||
});
|
||||
|
||||
nextStateBackedge.setValue(b.create<sv::ReadInOutOp>(loc, stateCaseMuxes[0]));
|
||||
|
||||
llvm::SmallVector<Value> outputPortAssignments;
|
||||
for (auto outputMux : llvm::makeArrayRef(stateCaseMuxes).drop_front())
|
||||
outputPortAssignments.push_back(
|
||||
b.create<sv::ReadInOutOp>(machineOp.getLoc(), outputMux));
|
||||
|
||||
// Delete the default created output op and replace it with the output muxes.
|
||||
auto *oldOutputOp = hwModuleOp.front().getTerminator();
|
||||
b.create<hw::OutputOp>(loc, outputPortAssignments);
|
||||
oldOutputOp->erase();
|
||||
|
||||
// Erase the original machine op.
|
||||
machineOp.erase();
|
||||
|
||||
return success();
|
||||
}
|
||||
|
||||
FailureOr<Value>
|
||||
MachineOpConverter::convertTransitions( // NOLINT(misc-no-recursion)
|
||||
StateOp currentState, ArrayRef<TransitionOp> transitions) {
|
||||
Value nextState;
|
||||
if (transitions.empty()) {
|
||||
// Base case - transition to the current state.
|
||||
nextState = encoding->encode(currentState);
|
||||
} else {
|
||||
// Recursive case - transition to a named state.
|
||||
auto transition = cast<fsm::TransitionOp>(transitions.front());
|
||||
nextState = encoding->encode(transition.getNextState());
|
||||
if (transition.hasGuard()) {
|
||||
// Not always taken; recurse and mux between the targeted next state and
|
||||
// the recursion result, selecting based on the provided guard.
|
||||
auto guardOpRes = moveOps(&transition.guard().front());
|
||||
if (failed(guardOpRes))
|
||||
return failure();
|
||||
|
||||
auto guard = cast<ReturnOp>(*guardOpRes).getOperand(0);
|
||||
auto otherNextState =
|
||||
convertTransitions(currentState, transitions.drop_front());
|
||||
if (failed(otherNextState))
|
||||
return failure();
|
||||
comb::MuxOp nextStateMux = b.create<comb::MuxOp>(
|
||||
transition.getLoc(), guard, nextState, *otherNextState);
|
||||
nextState = nextStateMux;
|
||||
}
|
||||
}
|
||||
|
||||
assert(nextState && "next state should be defined");
|
||||
return nextState;
|
||||
}
|
||||
|
||||
llvm::SmallVector<Value>
|
||||
MachineOpConverter::getOutputAssignments(StateConversionResults &convResults) {
|
||||
|
||||
// One for each output port.
|
||||
llvm::SmallVector<llvm::SmallDenseMap<StateOp, Value>> outputPortValues(
|
||||
machineOp.getNumResults());
|
||||
for (auto &state : orderedStates) {
|
||||
for (size_t portIndex = 0; portIndex < machineOp.getNumResults();
|
||||
portIndex++)
|
||||
outputPortValues[portIndex][state] =
|
||||
convResults[state].outputs[portIndex];
|
||||
}
|
||||
|
||||
llvm::SmallVector<Value> outputPortAssignments;
|
||||
|
||||
auto outputMuxes = buildStateCaseMux(
|
||||
machineOp.getLoc(), stateReg, outputPortValues, [&](size_t idx) {
|
||||
return b.getStringAttr("output_" + std::to_string(idx));
|
||||
});
|
||||
|
||||
for (auto outputMux : outputMuxes)
|
||||
outputPortAssignments.push_back(
|
||||
b.create<sv::ReadInOutOp>(machineOp.getLoc(), outputMux));
|
||||
|
||||
return outputPortAssignments;
|
||||
}
|
||||
|
||||
FailureOr<MachineOpConverter::StateConversionResult>
|
||||
MachineOpConverter::convertState(StateOp state) {
|
||||
MachineOpConverter::StateConversionResult res;
|
||||
|
||||
// 3.1) Convert the output region by moving the operations into the module
|
||||
// scope and gathering the operands of the output op.
|
||||
auto outputOpRes = moveOps(&state.output().front());
|
||||
if (failed(outputOpRes))
|
||||
return failure();
|
||||
|
||||
OutputOp outputOp = cast<fsm::OutputOp>(outputOpRes.getValue());
|
||||
res.outputs = outputOp.getOperands(); // 3.2
|
||||
|
||||
auto transitions = llvm::SmallVector<TransitionOp>(
|
||||
state.transitions().getOps<TransitionOp>());
|
||||
// 3.3, 3.4) Convert the transitions and record the next-state value
|
||||
// derived from the transitions being selected in a priority-encoded manner.
|
||||
auto nextStateRes = convertTransitions(state, transitions);
|
||||
if (failed(nextStateRes))
|
||||
return failure();
|
||||
res.nextState = nextStateRes.getValue();
|
||||
return res;
|
||||
}
|
||||
|
||||
struct FSMToSVPass : public ConvertFSMToSVBase<FSMToSVPass> {
|
||||
void runOnOperation() override;
|
||||
};
|
||||
|
||||
void FSMToSVPass::runOnOperation() {
|
||||
auto module = getOperation();
|
||||
auto b = OpBuilder(module);
|
||||
SmallVector<Operation *, 16> opToErase;
|
||||
|
||||
// Traverse all machines and convert.
|
||||
for (auto machine : llvm::make_early_inc_range(module.getOps<MachineOp>())) {
|
||||
MachineOpConverter converter(b, machine);
|
||||
|
||||
if (failed(converter.dispatch())) {
|
||||
signalPassFailure();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// Traverse all machine instances and convert to hw instances.
|
||||
llvm::SmallVector<HWInstanceOp> instances;
|
||||
module.walk([&](HWInstanceOp instance) { instances.push_back(instance); });
|
||||
for (auto instance : instances) {
|
||||
auto fsmHWModule = module.lookupSymbol<hw::HWModuleOp>(instance.machine());
|
||||
assert(fsmHWModule &&
|
||||
"FSM machine should have been converted to a hw.module");
|
||||
|
||||
b.setInsertionPoint(instance);
|
||||
llvm::SmallVector<Value, 4> operands;
|
||||
llvm::transform(instance.getOperands(), std::back_inserter(operands),
|
||||
[&](auto operand) { return operand; });
|
||||
auto hwInstance = b.create<hw::InstanceOp>(
|
||||
instance.getLoc(), fsmHWModule, b.getStringAttr(instance.getName()),
|
||||
operands, nullptr);
|
||||
instance.replaceAllUsesWith(hwInstance);
|
||||
instance.erase();
|
||||
}
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
std::unique_ptr<mlir::Pass> circt::createConvertFSMToSVPass() {
|
||||
return std::make_unique<FSMToSVPass>();
|
||||
}
|
||||
|
|
@ -90,6 +90,10 @@ namespace sv {
|
|||
class SVDialect;
|
||||
} // namespace sv
|
||||
|
||||
namespace fsm {
|
||||
class FSMDialect;
|
||||
} // namespace fsm
|
||||
|
||||
// Generate the classes which represent the passes
|
||||
#define GEN_PASS_CLASSES
|
||||
#include "circt/Conversion/Passes.h.inc"
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "mlir/IR/DialectImplementation.h"
|
||||
#include "mlir/IR/FunctionImplementation.h"
|
||||
#include "mlir/IR/PatternMatch.h"
|
||||
#include "llvm/Support/FormatVariadic.h"
|
||||
|
||||
using namespace mlir;
|
||||
using namespace circt;
|
||||
|
|
@ -59,7 +60,10 @@ void MachineOp::getHWPortInfo(SmallVectorImpl<hw::PortInfo> &ports) {
|
|||
|
||||
for (unsigned i = 0, e = machineType.getNumInputs(); i < e; ++i) {
|
||||
hw::PortInfo port;
|
||||
port.name = builder.getStringAttr("in" + std::to_string(i));
|
||||
if (argNames())
|
||||
port.name = argNames().getValue()[i].cast<StringAttr>();
|
||||
else
|
||||
port.name = builder.getStringAttr("in" + std::to_string(i));
|
||||
port.direction = circt::hw::PortDirection::INPUT;
|
||||
port.type = machineType.getInput(i);
|
||||
port.argNum = i;
|
||||
|
|
@ -68,7 +72,10 @@ void MachineOp::getHWPortInfo(SmallVectorImpl<hw::PortInfo> &ports) {
|
|||
|
||||
for (unsigned i = 0, e = machineType.getNumResults(); i < e; ++i) {
|
||||
hw::PortInfo port;
|
||||
port.name = builder.getStringAttr("out" + std::to_string(i));
|
||||
if (resNames())
|
||||
port.name = resNames().getValue()[i].cast<StringAttr>();
|
||||
else
|
||||
port.name = builder.getStringAttr("out" + std::to_string(i));
|
||||
port.direction = circt::hw::PortDirection::OUTPUT;
|
||||
port.type = machineType.getResult(i);
|
||||
port.argNum = i;
|
||||
|
|
@ -125,6 +132,22 @@ LogicalResult MachineOp::verify() {
|
|||
return emitOpError("initial state '" + initialState() +
|
||||
"' was not defined in the machine");
|
||||
|
||||
if (argNames() && argNames().getValue().size() != getArgumentTypes().size())
|
||||
return emitOpError() << "number of machine arguments ("
|
||||
<< getArgumentTypes().size()
|
||||
<< ") does "
|
||||
"not match the provided number "
|
||||
"of argument names ("
|
||||
<< argNames().getValue().size() << ")";
|
||||
|
||||
if (resNames() && resNames().getValue().size() != getResultTypes().size())
|
||||
return emitOpError() << "number of machine results ("
|
||||
<< getResultTypes().size()
|
||||
<< ") does "
|
||||
"not match the provided number "
|
||||
"of result names ("
|
||||
<< resNames().getValue().size() << ")";
|
||||
|
||||
return success();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -885,7 +885,7 @@ void CaseOp::print(OpAsmPrinter &p) {
|
|||
|
||||
LogicalResult CaseOp::verify() {
|
||||
if (!(hw::isHWIntegerType(getCond().getType()) ||
|
||||
getCond().getType().isa<hw::EnumType>()))
|
||||
hw::isHWEnumType(getCond().getType())))
|
||||
return emitError("condition must have either integer or enum type");
|
||||
|
||||
// Ensure that the number of regions and number of case values match.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,91 @@
|
|||
// RUN: circt-opt -split-input-file -convert-fsm-to-sv %s | FileCheck %s
|
||||
|
||||
fsm.machine @FSM(%arg0: i1, %arg1: i1) -> (i8) attributes {initialState = "A"} {
|
||||
%c_0 = hw.constant 0 : i8
|
||||
fsm.state @A output {
|
||||
fsm.output %c_0 : i8
|
||||
} transitions {
|
||||
fsm.transition @B
|
||||
}
|
||||
|
||||
fsm.state @B output {
|
||||
fsm.output %c_0 : i8
|
||||
} transitions {
|
||||
fsm.transition @A
|
||||
}
|
||||
}
|
||||
|
||||
// ----
|
||||
|
||||
// CHECK: hw.module @top(%arg0: i1, %arg1: i1, %clk: i1, %rst: i1) -> (out: i8) {
|
||||
// CHECK: %fsm_inst.out0 = hw.instance "fsm_inst" @FSM(in0: %arg0: i1, in1: %arg1: i1, clk: %clk: i1, rst: %rst: i1) -> (out0: i8)
|
||||
// CHECK: hw.output %fsm_inst.out0 : i8
|
||||
// CHECK: }
|
||||
hw.module @top(%arg0: i1, %arg1: i1, %clk : i1, %rst : i1) -> (out: i8) {
|
||||
%out = fsm.hw_instance "fsm_inst" @FSM(%arg0, %arg1), clock %clk, reset %rst : (i1, i1) -> (i8)
|
||||
hw.output %out : i8
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
// CHECK-LABEL: hw.type_scope @top_enum_typedecls {
|
||||
// CHECK-NEXT: hw.typedecl @top_state_t : !hw.enum<A, B>
|
||||
// CHECK-NEXT: }
|
||||
|
||||
// CHECK-LABEL: hw.module @top(%a0: i1, %a1: i1, %clk: i1, %rst: i1) -> (r0: i8, r1: i8) {
|
||||
// CHECK-NEXT: %A = hw.enum.constant A : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: %to_A = sv.wire sym @A : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: sv.assign %to_A, %A : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: %0 = sv.read_inout %to_A : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: %B = hw.enum.constant B : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: %to_B = sv.wire sym @B : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: sv.assign %to_B, %B : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: %1 = sv.read_inout %to_B : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: %state_reg = seq.compreg %4, %clk, %rst, %0 : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: %c42_i8 = hw.constant 42 : i8
|
||||
// CHECK-NEXT: %c0_i8 = hw.constant 0 : i8
|
||||
// CHECK-NEXT: %c1_i8 = hw.constant 1 : i8
|
||||
// CHECK-NEXT: %2 = comb.and %a0, %a1 : i1
|
||||
// CHECK-NEXT: %3 = comb.mux %2, %0, %1 : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: sv.alwayscomb {
|
||||
// CHECK-NEXT: sv.case %state_reg : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: case A: {
|
||||
// CHECK-NEXT: sv.bpassign %next_state, %1 : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: sv.bpassign %output_0, %c0_i8 : i8
|
||||
// CHECK-NEXT: sv.bpassign %output_1, %c42_i8 : i8
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: case B: {
|
||||
// CHECK-NEXT: sv.bpassign %next_state, %3 : !hw.typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>
|
||||
// CHECK-NEXT: sv.bpassign %output_0, %c1_i8 : i8
|
||||
// CHECK-NEXT: sv.bpassign %output_1, %c42_i8 : i8
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: }
|
||||
// CHECK-NEXT: %next_state = sv.reg : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: %output_0 = sv.reg : !hw.inout<i8>
|
||||
// CHECK-NEXT: %output_1 = sv.reg : !hw.inout<i8>
|
||||
// CHECK-NEXT: %4 = sv.read_inout %next_state : !hw.inout<typealias<@top_enum_typedecls::@top_state_t, !hw.enum<A, B>>>
|
||||
// CHECK-NEXT: %5 = sv.read_inout %output_0 : !hw.inout<i8>
|
||||
// CHECK-NEXT: %6 = sv.read_inout %output_1 : !hw.inout<i8>
|
||||
// CHECK-NEXT: hw.output %5, %6 : i8, i8
|
||||
// CHECK-NEXT: }
|
||||
|
||||
|
||||
fsm.machine @top(%a0: i1, %arg1: i1) -> (i8, i8) attributes {initialState = "A", argNames = ["a0", "a1"], resNames = ["r0", "r1"]} {
|
||||
%c_42 = hw.constant 42 : i8
|
||||
fsm.state @A output {
|
||||
%c_0 = hw.constant 0 : i8
|
||||
fsm.output %c_0, %c_42 : i8, i8
|
||||
} transitions {
|
||||
fsm.transition @B
|
||||
}
|
||||
|
||||
fsm.state @B output {
|
||||
%c_1 = hw.constant 1 : i8
|
||||
fsm.output %c_1, %c_42 : i8, i8
|
||||
} transitions {
|
||||
fsm.transition @A guard {
|
||||
%g = comb.and %a0, %arg1 : i1
|
||||
fsm.return %g
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
// RUN: circt-opt -split-input-file -convert-fsm-to-sv -verify-diagnostics %s
|
||||
|
||||
|
||||
fsm.machine @foo(%arg0: i1) -> () attributes {initialState = "A"} {
|
||||
// expected-error@+1 {{'fsm.variable' op FSM variables not yet supported for SV lowering.}}
|
||||
%cnt = fsm.variable "cnt" {initValue = 0 : i16} : i16
|
||||
|
||||
fsm.state @A output {
|
||||
fsm.output
|
||||
} transitions {
|
||||
fsm.transition @A
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
fsm.machine @foo(%arg0: i1) -> (i1) attributes {initialState = "A"} {
|
||||
// expected-error@+1 {{'arith.constant' op is unsupported (op from the arith dialect).}}
|
||||
%true = arith.constant true
|
||||
fsm.state @A output {
|
||||
fsm.output %true : i1
|
||||
} transitions {
|
||||
fsm.transition @A
|
||||
}
|
||||
|
||||
fsm.state @B output {
|
||||
fsm.output %true : i1
|
||||
} transitions {
|
||||
fsm.transition @A
|
||||
}
|
||||
}
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
// CHECK: }
|
||||
// CHECK: hw.module @bar(%clk: i1, %rst_n: i1) {
|
||||
// CHECK: %true = hw.constant true
|
||||
// CHECK: %0 = fsm.hw_instance "foo_inst" @foo(%true) : (i1) -> i1, clock %clk : i1, reset %rst_n : i1
|
||||
// CHECK: %0 = fsm.hw_instance "foo_inst" @foo(%true), clock %clk, reset %rst_n : (i1) -> i1
|
||||
// CHECK: hw.output
|
||||
// CHECK: }
|
||||
// CHECK: func @qux() {
|
||||
|
|
@ -91,7 +91,7 @@ fsm.machine @foo(%arg0: i1) -> i1 attributes {initialState = "IDLE"} {
|
|||
// Hardware-style instantiation.
|
||||
hw.module @bar(%clk: i1, %rst_n: i1) {
|
||||
%in = hw.constant true
|
||||
%out = fsm.hw_instance "foo_inst" @foo(%in) : (i1) -> i1, clock %clk : i1, reset %rst_n : i1
|
||||
%out = fsm.hw_instance "foo_inst" @foo(%in), clock %clk, reset %rst_n : (i1) -> i1
|
||||
}
|
||||
|
||||
// Software-style instantiation and triggering.
|
||||
|
|
|
|||
|
|
@ -66,3 +66,18 @@ fsm.machine @foo(%arg0: i1) -> i1 attributes {initialState = "IDLE"} {
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
// expected-error @+1 {{'fsm.machine' op number of machine arguments (1) does not match the provided number of argument names (2)}}
|
||||
fsm.machine @foo(%arg0: i1) -> i1 attributes {initialState = "IDLE", argNames = ["in0", "in1"]} {
|
||||
fsm.state @IDLE output {} transitions {}
|
||||
}
|
||||
|
||||
// -----
|
||||
|
||||
// expected-error @+1 {{'fsm.machine' op number of machine results (1) does not match the provided number of result names (2)}}
|
||||
fsm.machine @foo(%arg0: i1) -> i1 attributes {initialState = "IDLE", resNames = ["out0", "out1"]} {
|
||||
fsm.state @IDLE output {} transitions {}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ target_link_libraries(circt-opt
|
|||
CIRCTFIRRTLTransforms
|
||||
CIRCTFSM
|
||||
CIRCTFSMTransforms
|
||||
CIRCTFSMToSV
|
||||
CIRCTHandshake
|
||||
CIRCTHandshakeToFIRRTL
|
||||
CIRCTHandshakeToHW
|
||||
|
|
|
|||
Loading…
Reference in New Issue