mirror of https://github.com/llvm/circt.git
[FIRRTL] Move intrinsics into their own tablegen file
This commit is contained in:
Nandor Licker
parent
3ce5c8c5b9
commit
36eaec3fa1
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@ -21,6 +21,7 @@ include "FIRRTLStructure.td"
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include "FIRRTLDeclarations.td"
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include "FIRRTLStatements.td"
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include "FIRRTLExpressions.td"
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include "FIRRTLIntrinsics.td"
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// Types
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include "FIRRTLTypes.td"
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@ -865,77 +865,6 @@ def Mux4CellIntrinsicOp : PrimOp<"int.mux4cell"> {
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"`(` operands `)` attr-dict `:` functional-type(operands, $result)";
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}
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//===----------------------------------------------------------------------===//
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// Verif and SV specific
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//===----------------------------------------------------------------------===//
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def IsXIntrinsicOp : FIRRTLOp<"int.isX",
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[HasCustomSSAName, Pure]> {
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let summary = "Test for 'x";
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let description = [{
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The `int.isX` expression checks that the operand is not a verilog literal
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'x. FIRRTL doesn't have a notion of 'x per-se, but x can come in to the
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system from external modules and from SV constructs. Verification
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constructs need to explicitly test for 'x.
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}];
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let arguments = (ins FIRRTLBaseType:$arg);
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let results = (outs NonConstUInt1Type:$result);
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let hasFolder = 1;
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let assemblyFormat = "$arg attr-dict `:` type($arg)";
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}
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def PlusArgsTestIntrinsicOp : FIRRTLOp<"int.plusargs.test",
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[HasCustomSSAName, Pure]> {
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let summary = "SystemVerilog `$test$plusargs` call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs NonConstUInt1Type:$found);
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let assemblyFormat = "$formatString attr-dict";
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}
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def PlusArgsValueIntrinsicOp : FIRRTLOp<"int.plusargs.value",
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[HasCustomSSAName, Pure]> {
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let summary = "SystemVerilog `$value$plusargs` call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs NonConstUInt1Type:$found, AnyType:$result);
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let assemblyFormat = "$formatString attr-dict `:` type($result)";
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}
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def HasBeenResetIntrinsicOp : FIRRTLOp<"int.has_been_reset", [Pure]> {
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let summary = "Check that a proper reset has been seen.";
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let description = [{
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The result of `firrtl.int.has_been_reset` reads as 0 immediately after simulation
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startup and after each power-cycle in a power-aware simulation. The result
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remains 0 before and during reset and only switches to 1 after the reset is
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deasserted again.
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See the corresponding `verif.has_been_reset` operation.
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}];
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let arguments = (ins NonConstClockType:$clock, AnyResetType:$reset);
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let results = (outs NonConstUInt1Type:$result);
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let hasFolder = 1;
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let assemblyFormat = "$clock `,` $reset attr-dict `:` type($reset)";
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}
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def FPGAProbeIntrinsicOp : FIRRTLOp<"int.fpga_probe", []> {
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let summary = "Mark a value to be observed through FPGA debugging facilities";
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let description = [{
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The `firrtl.int.fpga_probe` intrinsic marks a value in
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the IR to be made observable through FPGA debugging facilities. Most FPGAs
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offer a form of signal observation or logic analyzer to debug a design. This
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operation allows the IR to indicate which signals should be made observable
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for debugging. Later FPGA-specific passes may then pick this information up
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and materialize the necessary logic analyzers or tool scripts.
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}];
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let arguments = (ins AnyType:$input, NonConstClockType:$clock);
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let results = (outs);
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let assemblyFormat = "$clock `,` $input attr-dict `:` type($input)";
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}
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//===----------------------------------------------------------------------===//
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// Verbatim
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//===----------------------------------------------------------------------===//
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@ -1012,7 +941,7 @@ def VerbatimWireOp : FIRRTLOp<"verbatim.wire",
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//===----------------------------------------------------------------------===//
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// This assumes operands are ground types without explicitly checking
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class SameGroundTypeOperandConstness<string a, string b>
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class SameGroundTypeOperandConstness<string a, string b>
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: PredOpTrait<
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"operand constness must match",
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CPred<"isConst($" # a # ".getType()) == isConst($" # b # ".getType())">>;
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@ -0,0 +1,82 @@
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//===- FIRRTLIntrinsics.td - FIRRTL intrinsic ops ----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the MLIR ops for FIRRTL intrinsics.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
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#define CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
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def IsXIntrinsicOp : FIRRTLOp<"int.isX",
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[HasCustomSSAName, Pure]> {
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let summary = "Test for 'x";
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let description = [{
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The `int.isX` expression checks that the operand is not a verilog literal
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'x. FIRRTL doesn't have a notion of 'x per-se, but x can come in to the
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system from external modules and from SV constructs. Verification
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constructs need to explicitly test for 'x.
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}];
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let arguments = (ins FIRRTLBaseType:$arg);
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let results = (outs NonConstUInt1Type:$result);
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let hasFolder = 1;
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let assemblyFormat = "$arg attr-dict `:` type($arg)";
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}
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def PlusArgsTestIntrinsicOp : FIRRTLOp<"int.plusargs.test",
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[HasCustomSSAName, Pure]> {
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let summary = "SystemVerilog `$test$plusargs` call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs NonConstUInt1Type:$found);
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let assemblyFormat = "$formatString attr-dict";
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}
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def PlusArgsValueIntrinsicOp : FIRRTLOp<"int.plusargs.value",
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[HasCustomSSAName, Pure]> {
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let summary = "SystemVerilog `$value$plusargs` call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs NonConstUInt1Type:$found, AnyType:$result);
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let assemblyFormat = "$formatString attr-dict `:` type($result)";
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}
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def HasBeenResetIntrinsicOp : FIRRTLOp<"int.has_been_reset", [Pure]> {
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let summary = "Check that a proper reset has been seen.";
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let description = [{
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The result of `firrtl.int.has_been_reset` reads as 0 immediately after simulation
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startup and after each power-cycle in a power-aware simulation. The result
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remains 0 before and during reset and only switches to 1 after the reset is
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deasserted again.
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See the corresponding `verif.has_been_reset` operation.
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}];
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let arguments = (ins NonConstClockType:$clock, AnyResetType:$reset);
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let results = (outs NonConstUInt1Type:$result);
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let hasFolder = 1;
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let assemblyFormat = "$clock `,` $reset attr-dict `:` type($reset)";
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}
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def FPGAProbeIntrinsicOp : FIRRTLOp<"int.fpga_probe", []> {
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let summary = "Mark a value to be observed through FPGA debugging facilities";
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let description = [{
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The `firrtl.int.fpga_probe` intrinsic marks a value in
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the IR to be made observable through FPGA debugging facilities. Most FPGAs
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offer a form of signal observation or logic analyzer to debug a design. This
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operation allows the IR to indicate which signals should be made observable
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for debugging. Later FPGA-specific passes may then pick this information up
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and materialize the necessary logic analyzers or tool scripts.
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}];
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let arguments = (ins AnyType:$input, NonConstClockType:$clock);
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let results = (outs);
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let assemblyFormat = "$clock `,` $input attr-dict `:` type($input)";
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}
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#endif // CIRCT_DIALECT_FIRRTL_FIRRTLINTRINSICS_TD
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