diff --git a/docs/dialects.drawio b/docs/dialects.drawio index 7ddc6770fd..4defe85f0e 100644 --- a/docs/dialects.drawio +++ b/docs/dialects.drawio @@ -1,16 +1,16 @@ - + - + - + - + @@ -113,7 +113,7 @@ - + diff --git a/docs/dialects.png b/docs/dialects.png index f3ed3520bc..3d7b843e0d 100644 Binary files a/docs/dialects.png and b/docs/dialects.png differ diff --git a/docs/dialects.svg b/docs/dialects.svg index c468677729..57dd3ad81a 100644 --- a/docs/dialects.svg +++ b/docs/dialects.svg @@ -1,2 +1,3 @@ + -
High FIRRTL
High FIRRTL
Mid FIRRTL
Mid FIRRTL
Low FIRRTL
Low FIRRTL
Structural LLHD
Structural LLHD
RTL
RTL
SV
SV
EmitVerilog
EmitVerilog
Handshake
Handshake
1.
1.
1.
1.
2.
2.
2.
2.
1. Handshake to FIRRTL
2. Lowering within FIRRTL (hypothetical)
3. FIRRTL to LLHD
4. FIRRTL to RTL
5. Mid FIRRTL to RTL (hypothetical)
6. Mid FIRRTL to SV (hypothetical)
7. EmitVerilog
8. Desequentialization / Process Lowering
9. LLHD to LLVM (simulation model)
10. LLHD to RTL promotion (hypothetical; fallible)
11. RTL to LLHD (hypothetical)
12. Likely almost identical; eventually merge?
1. Handshake to FIRRTL...
3.
3.
4.
4.
5.
5.
6.
6.
7.
7.
7.
7.
7.
7.
SV File
SV File
llhd-sim
llhd-sim
VCD Trace
VCD Trace
Moore
Moore
Behavioural LLHD
Behavioural LLHD
SV/VHDL
File
SV/VHDL...
FIR File
FIR File
FIRRTL Parser
FIRRTL Parser
8.
8.
RTL and Testbench
RTL and Te...
9.
9.
10.
10.
11.
11.
12.
12.
12.
12.
circilator
circilator
CPP File
CPP FileViewer does not support full SVG 1.1 \ No newline at end of file +
High FIRRTL
High FIRRTL
Mid FIRRTL
Mid FIRRTL
Low FIRRTL
Low FIRRTL
Structural LLHD
Structural LLHD
RTL
RTL
SV
SV
EmitVerilog
EmitVerilog
Handshake
Handshake
1.
1.
1.
1.
2.
2.
2.
2.
1. Handshake to FIRRTL
2. Lowering within FIRRTL
3. FIRRTL to LLHD
4. FIRRTL to RTL
5. Mid FIRRTL to RTL (hypothetical)
6. Mid FIRRTL to SV (hypothetical)
7. EmitVerilog
8. Desequentialization / Process Lowering
9. LLHD to LLVM (simulation model)
10. LLHD to RTL promotion (hypothetical; fallible)
11. RTL to LLHD (hypothetical)
12. Likely almost identical; eventually merge?
1. Handshake to FIRRTL...
3.
3.
4.
4.
5.
5.
6.
6.
7.
7.
7.
7.
7.
7.
SV File
SV File
llhd-sim
llhd-sim
VCD Trace
VCD Trace
Moore
Moore
Behavioural LLHD
Behavioural LLHD
SV/VHDL
File
SV/VHDL...
FIR File
FIR File
FIRRTL Parser
FIRRTL Parser
8.
8.
RTL and Testbench
RTL and Te...
9.
9.
10.
10.
11.
11.
12.
12.
12.
12.
circilator
circilator
CPP File
CPP FileViewer does not support full SVG 1.1 \ No newline at end of file