mirror of https://github.com/llvm/circt.git
[FIRRTL] Add support for "intrinsics" (#4429)
Add support for intrinsics in FIRRTL. Until intrinsics are supported in the firrtl spec, or we have more complex intrinsics, do direct lowering of intrinsics into their ops. It is expected that eventually something like an "intmodule" will exist and annotated extern modules will not be used for intrinsics or first they will lower to intmodules internally, then intmodules will be handled uniformly. As an example, add a sizeof operator which returns the number of bits in the argument type. This let's you query the result of type inference from inside the circuit. Also adds support for isX as an intrinsic and plusarg sv functions.
This commit is contained in:
Andrew Lenharth
GitHub
parent
02d124584f
commit
316421a20b
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@ -771,6 +771,19 @@ Example:
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}
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```
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### circt.intrinsic
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| Property | Type | Description |
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| ---------- | ------ | ------------- |
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| class | string | `circt.intrinsic` |
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| target | string | Reference target |
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| intrinsic | string | Name of Intrinsic |
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Used to indicate an external module is really an intrinsic module. This exists
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to allow a frontend to generate intrinsics without firrtl language support for
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intrinsics. It is expect this will be deprecated as soon as the firrtl language
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supports intrinsics. This annotation can only be local and applied to a module.
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### SitestBlackBoxAnnotation
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| Property | Type | Description |
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@ -1474,3 +1487,4 @@ modules' bind file. This attribute has type `OutputFileAttr`.
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Used by SVExtractTestCode. Indicates a module whose instances should be
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extracted from the circuit in the indicated extraction type.
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@ -0,0 +1,78 @@
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# Intrinsics
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Intrinsics provide an implementation-specific way to extend the firrtl language
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with new operations.
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Intrinsics are currently implemented as annotated external modules. We expect
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that native firrtl support for intrinsics will be added to the language.
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## Motivation
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Intrinsics provide a way to add functionality to firrtl without having to extend
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the firrtl language. This allows a fast path for prototyping new operations to
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rapidly repsond to output requirements. Intrinsics maintain strict definitions
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and type checking.
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## Supported Intrinsics
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Annotations here are written in their JSON format. A "reference target"
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indicates that the annotation could target any object in the hierarchy,
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although there may be further restrictions in the annotation.
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### circt.sizeof
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Returns the size of a type. The input port is not read from and may be any
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type, including uninfered types.
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| Parameter | Type | Description |
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| ---------- | ------ | ------------- |
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| Port | Direction | Type | Description |
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| ---------- | --------- | -------- | ----------------------------------- |
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| i | input | Any | value whose type is to be returned |
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| size | output | UInt<32> | Size of type of i |
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### circt.isX
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Tests if the value is a literal `x`. Firrtl doesn't have a notion of 'x per-se,
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but x can come in to the system from external modules and from SV constructs.
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Verification constructs need to explicitly test for 'x.
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| Parameter | Type | Description |
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| ---------- | ------ | ------------- |
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| Port | Direction | Type | Description |
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| ---------- | --------- | -------- | ----------------------------------- |
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| i | input | Any | value test |
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| found | output | UInt<1> | i is `x` |
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### circt.plusargs.value
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Tests and extracts a value from simulator command line options with system
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verilog $value$plusargs. This is described in SystemVerilog 2012 section 21.6.
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We do not currently check that the format string substitution flag matches the
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type of the result.
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| Parameter | Type | Description |
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| ---------- | ------ | ------------- |
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| FORMAT | string | Format string per SV 21.6 |
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| Port | Direction | Type | Description |
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| ---------- | --------- | -------- | ----------------------------------- |
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| found | output | UInt<1> | found in args |
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| result | output | AnyType | found in args |
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### circt.plusargs.test
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Tests simulator command line options with system verilog $test$plusargs. This
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is described in SystemVerilog 2012 section 21.6.
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| Parameter | Type | Description |
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| ---------- | ------ | ------------- |
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| FORMAT | string | Format string per SV 21.6 |
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| Port | Direction | Type | Description |
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| ---------- | --------- | -------- | ----------------------------------- |
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| found | output | UInt<1> | found in args |
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@ -1064,3 +1064,17 @@ b <= mux(cond, a, inv)
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It follows that interpretation (4) will then convert the false leg of the `mux`
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to a constant zero.
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## Intrinsics
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Intrinsics are implementation-defined constructs. Intrinsics provide a way to
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extend the system with funcitonality without changing the langauge. They form
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an implementation-specific built-in library. Unlike traditional libraries,
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implementations of intrinsics have access to internals of the compiler, allowing
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them to implement features not possible in the language.
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In FIRRTL, we support intrinsic modules. The internal op is `firrtl.intmodule`
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which has all the properties of an external module. Until the firrtl spec
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supports intrinsics, intrinsic modules are expressed in firrtl as external
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modules with the `circt.intrinsic` annotation on the module.
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@ -473,6 +473,8 @@ class UnaryPrimOp<string mnemonic, Type srcType, Type resultType,
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let parseValidator = "impl::validateUnaryOpArguments";
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}
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def SizeOfIntrinsicOp : UnaryPrimOp<"int.sizeof", FIRRTLBaseType, UInt32Type>;
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def AsSIntPrimOp : UnaryPrimOp<"asSInt", FIRRTLBaseType, SIntType>;
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def AsUIntPrimOp : UnaryPrimOp<"asUInt", FIRRTLBaseType, UIntType>;
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def AsAsyncResetPrimOp
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@ -613,10 +615,10 @@ def TailPrimOp : PrimOp<"tail"> {
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// Verif and SV specific
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//===----------------------------------------------------------------------===//
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def IsXVerifOp : FIRRTLExprOp<"verif_isX"> {
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def IsXIntrinsicOp : FIRRTLExprOp<"int.isX"> {
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let summary = "Test for 'x";
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let description = [{
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The verif.isX expression checks that the operand is not a verilog literal
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The int.isX expression checks that the operand is not a verilog literal
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'x. Firrtl doesn't have a notion of 'x per-se, but x can come in to the
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system from external modules and from SV constructs. Verification
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constructs need to explicitly test for 'x.
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@ -624,9 +626,25 @@ def IsXVerifOp : FIRRTLExprOp<"verif_isX"> {
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let arguments = (ins FIRRTLBaseType:$arg);
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let results = (outs UInt1Type:$result);
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let assemblyFormat =
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"$arg attr-dict `:` qualified(type($arg))";
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let hasFolder = 1;
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let assemblyFormat = "$arg attr-dict `:` type($arg)";
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}
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def PlusArgsTestIntrinsicOp : FIRRTLExprOp<"int.plusargs.test"> {
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let summary = "Verilog $test$plusargs call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs UInt1Type:$found);
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let assemblyFormat = "$formatString attr-dict";
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}
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def PlusArgsValueIntrinsicOp
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: FIRRTLOp<"int.plusargs.value", [HasCustomSSAName, Pure]> {
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let summary = "Verilog $value$plusargs call";
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let arguments = (ins StrAttr:$formatString);
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let results = (outs UInt1Type:$found, AnyType:$result);
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let assemblyFormat = "$formatString attr-dict `:` type($result)";
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}
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//===----------------------------------------------------------------------===//
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@ -105,7 +105,7 @@ def FExtModuleOp : FIRRTLOp<"extmodule",
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[IsolatedFromAbove, Symbol, HasParent<"CircuitOp">, OpAsmOpInterface,
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DeclareOpInterfaceMethods<FModuleLike>, InnerSymbolTable,
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DeclareOpInterfaceMethods<HWModuleLike>]> {
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let summary = "FIRRTL extmodule";
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let summary = "FIRRTL external module";
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let description = [{
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The "firrtl.extmodule" operation represents an external reference to a
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Verilog module, including a given name and a list of ports.
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@ -147,7 +147,7 @@ def FMemModuleOp : FIRRTLOp<"memmodule",
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[IsolatedFromAbove, Symbol, HasParent<"CircuitOp">, OpAsmOpInterface,
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DeclareOpInterfaceMethods<FModuleLike>, InnerSymbolTable,
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DeclareOpInterfaceMethods<HWModuleLike>]> {
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let summary = "FIRRTL Generated Module";
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let summary = "FIRRTL Generated Memory Module";
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let description = [{
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The "firrtl.memmodule" operation represents an external reference to a
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memory module. See the "firrtl.mem" op for a deeper explantation of the
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@ -102,6 +102,12 @@ def UInt1Type : FIRRTLDialectType<
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"UInt<1> or UInt", "::circt::firrtl::UIntType">,
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BuildableType<"UIntType::get($_builder.getContext(), 1)">;
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def UInt32Type : FIRRTLDialectType<
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CPred<"$_self.isa<UIntType>() && "
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"$_self.cast<UIntType>().getWidth() == 32">,
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"UInt<32>", "::circt::firrtl::UIntType">,
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BuildableType<"UIntType::get($_builder.getContext(), 32)">;
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def AsyncResetType : FIRRTLDialectType<
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CPred<"$_self.isa<AsyncResetType>()">,
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"AsyncReset", "::circt::firrtl::AsyncResetType">,
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@ -43,8 +43,8 @@ public:
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// Unary operators.
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AsSIntPrimOp, AsUIntPrimOp, AsAsyncResetPrimOp, AsClockPrimOp,
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CvtPrimOp, NegPrimOp, NotPrimOp, AndRPrimOp, OrRPrimOp, XorRPrimOp,
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// Verif Expressions.
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IsXVerifOp,
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// Intrinsic Expressions.
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IsXIntrinsicOp, PlusArgsValueIntrinsicOp, PlusArgsTestIntrinsicOp,
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// Miscellaneous.
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BitsPrimOp, HeadPrimOp, MuxPrimOp, PadPrimOp, ShlPrimOp, ShrPrimOp,
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TailPrimOp, VerbatimExprOp, HWStructCastOp, BitCastOp, RefSendOp,
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@ -134,8 +134,10 @@ public:
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HANDLE(OrRPrimOp, Unary);
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HANDLE(XorRPrimOp, Unary);
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// Verif Expr.
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HANDLE(IsXVerifOp, Unhandled);
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// Intrinsic Expr.
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HANDLE(IsXIntrinsicOp, Unhandled);
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HANDLE(PlusArgsValueIntrinsicOp, Unhandled);
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HANDLE(PlusArgsTestIntrinsicOp, Unhandled);
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// Miscellaneous.
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HANDLE(BitsPrimOp, Unhandled);
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@ -54,6 +54,8 @@ std::unique_ptr<mlir::Pass> createLowerBundleVectorTypesPass();
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std::unique_ptr<mlir::Pass> createLowerCHIRRTLPass();
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std::unique_ptr<mlir::Pass> createLowerIntrinsicsPass();
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std::unique_ptr<mlir::Pass> createIMConstPropPass();
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std::unique_ptr<mlir::Pass>
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@ -609,6 +609,15 @@ def LowerXMR : Pass<"firrtl-lower-xmr", "firrtl::CircuitOp"> {
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let constructor = "circt::firrtl::createLowerXMRPass()";
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}
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def LowerIntrinsics : Pass<"firrtl-lower-intrinsics", "firrtl::CircuitOp"> {
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let summary = "Lower intrinsics";
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let description = [{
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This pass lowers intrinsics encoded as extmodule with annotation and
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intmodule to their implementation or op.
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}];
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let constructor = "circt::firrtl::createLowerIntrinsicsPass()";
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}
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def ResolveTraces : Pass<"firrtl-resolve-traces", "firrtl::CircuitOp"> {
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let summary = "Write out TraceAnnotations to an output annotation file";
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let description = [{
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@ -1609,7 +1609,7 @@ struct FIRRTLLowering : public FIRRTLVisitor<FIRRTLLowering, LogicalResult> {
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}
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// Verif Operations
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LogicalResult visitExpr(IsXVerifOp op);
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LogicalResult visitExpr(IsXIntrinsicOp op);
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// Other Operations
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LogicalResult visitExpr(BitsPrimOp op);
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@ -3370,7 +3370,7 @@ LogicalResult FIRRTLLowering::visitExpr(CatPrimOp op) {
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// Verif Operations
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//===----------------------------------------------------------------------===//
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LogicalResult FIRRTLLowering::visitExpr(IsXVerifOp op) {
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LogicalResult FIRRTLLowering::visitExpr(IsXIntrinsicOp op) {
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auto input = getLoweredValue(op.getArg());
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if (!input)
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return failure();
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@ -888,6 +888,21 @@ LogicalResult NEQPrimOp::canonicalize(NEQPrimOp op, PatternRewriter &rewriter) {
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// Unary Operators
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//===----------------------------------------------------------------------===//
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OpFoldResult SizeOfIntrinsicOp::fold(llvm::ArrayRef<mlir::Attribute>) {
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auto base = getInput().getType().cast<FIRRTLBaseType>();
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auto w = base.getBitWidthOrSentinel();
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if (w >= 0)
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return getIntAttr(getType(), APInt(32, w));
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return {};
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}
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OpFoldResult IsXIntrinsicOp::fold(llvm::ArrayRef<mlir::Attribute> operands) {
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// No constant can be 'x' by definition.
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if (auto cst = getConstant(operands[0]))
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return getIntAttr(getType(), APInt(1, 0));
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return {};
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}
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OpFoldResult AsSIntPrimOp::fold(ArrayRef<Attribute> operands) {
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// No effect.
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if (getInput().getType() == getType())
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@ -2903,6 +2903,11 @@ LogicalResult impl::validateUnaryOpArguments(ValueRange operands,
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return success();
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}
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FIRRTLType SizeOfIntrinsicOp::inferUnaryReturnType(FIRRTLType arg,
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Optional<Location> loc) {
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return UIntType::get(arg.getContext(), 32);
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}
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FIRRTLType AsSIntPrimOp::inferUnaryReturnType(FIRRTLType input,
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Optional<Location> loc) {
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auto base = input.dyn_cast<FIRRTLBaseType>();
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@ -3316,12 +3321,19 @@ FIRRTLType TailPrimOp::inferReturnType(ValueRange operands,
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// Verif Expressions
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//===----------------------------------------------------------------------===//
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FIRRTLType IsXVerifOp::inferReturnType(ValueRange operands,
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ArrayRef<NamedAttribute> attrs,
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Optional<Location> loc) {
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FIRRTLType IsXIntrinsicOp::inferReturnType(ValueRange operands,
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ArrayRef<NamedAttribute> attrs,
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Optional<Location> loc) {
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return UIntType::get(operands[0].getContext(), 1);
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}
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FIRRTLType
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PlusArgsTestIntrinsicOp::inferReturnType(ValueRange operands,
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ArrayRef<NamedAttribute> attrs,
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Optional<Location> loc) {
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return UIntType::get(attrs[0].getName().getContext(), 1);
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}
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//===----------------------------------------------------------------------===//
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// VerbatimExprOp
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//===----------------------------------------------------------------------===//
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@ -3975,6 +3987,9 @@ void AndRPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void SizeOfIntrinsicOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void AsAsyncResetPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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@ -4020,13 +4035,19 @@ void GTPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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void HeadPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void IsXVerifOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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void IsXIntrinsicOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void PlusArgsValueIntrinsicOp::getAsmResultNames(
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OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void PlusArgsTestIntrinsicOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void LEQPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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void LTPrimOp::getAsmResultNames(OpAsmSetValueNameFn setNameFn) {
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genericAsmResultNames(*this, setNameFn);
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}
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@ -3012,7 +3012,7 @@ ParseResult FIRCircuitParser::parseModule(CircuitOp circuit,
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// Otherwise, handle extmodule specific features like parameters.
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// Parse a defname if present.
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// Parse a defname if present and is an extmodule.
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// TODO(firrtl spec): defname isn't documented at all, what is it?
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StringRef defName;
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if (consumeIf(FIRToken::kw_defname)) {
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@ -404,7 +404,7 @@ ParseResult circt::firrtl::foldWhenEncodedVerifOp(PrintFOp printOp) {
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// Construct a `!whenCond | (value !== 1'bx)` predicate.
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Value notCond = predicate;
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predicate = builder.create<XorRPrimOp>(printOp.getSubstitutions()[0]);
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predicate = builder.create<IsXVerifOp>(predicate);
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predicate = builder.create<IsXIntrinsicOp>(predicate);
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predicate = builder.create<NotPrimOp>(predicate);
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predicate = builder.create<OrPrimOp>(notCond, predicate);
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}
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@ -21,6 +21,7 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms
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InnerSymbolDCE.cpp
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LowerAnnotations.cpp
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LowerCHIRRTL.cpp
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LowerIntrinsics.cpp
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LowerMemory.cpp
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LowerTypes.cpp
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LowerXMR.cpp
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@ -236,7 +236,7 @@ static LogicalResult applyWithoutTargetImpl(const AnnoPathValue &target,
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}
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/// An applier which puts the annotation on the target and drops the 'target'
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/// field from the annotaiton. Optionally handles non-local annotations.
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/// field from the annotation. Optionally handles non-local annotations.
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/// Ensures the target resolves to an expected type of operation.
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template <bool allowNonLocal, bool allowPortAnnoTarget, typename T,
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typename... Tr>
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@ -294,9 +294,9 @@ struct AnnoRecord {
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/// the FIRRTL Circuit, i.e., an Annotation which has no target. Historically,
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/// NoTargetAnnotations were used to control the Scala FIRRTL Compiler (SFC) or
|
||||
/// its passes, e.g., to set the output directory or to turn on a pass.
|
||||
/// Examplesof these in the SFC are "firrtl.options.TargetDirAnnotation" to set
|
||||
/// Examples of these in the SFC are "firrtl.options.TargetDirAnnotation" to set
|
||||
/// the output directory or "firrtl.stage.RunFIRRTLTransformAnnotation" to
|
||||
/// casuse the SFC to schedule a specified pass. Instead of leaving these
|
||||
/// cause the SFC to schedule a specified pass. Instead of leaving these
|
||||
/// floating or attaching them to the top-level MLIR module (which is a purer
|
||||
/// interpretation of "no target"), we choose to attach them to the Circuit even
|
||||
/// they do not "apply" to the Circuit. This gives later passes a common place,
|
||||
|
|
@ -313,6 +313,7 @@ static const llvm::StringMap<AnnoRecord> annotationRecords{{
|
|||
{"circt.testLocalOnly", {stdResolve, applyWithoutTarget<>}},
|
||||
{"circt.testNT", {noResolve, applyWithoutTarget<>}},
|
||||
{"circt.missing", {tryResolve, applyWithoutTarget<true>}},
|
||||
{"circt.intrinsic", {stdResolve, applyWithoutTarget<false, FExtModuleOp>}},
|
||||
// Grand Central Views/Interfaces Annotations
|
||||
{extractGrandCentralClass, NoTargetAnnotation},
|
||||
{grandCentralHierarchyFileAnnoClass, NoTargetAnnotation},
|
||||
|
|
|
|||
|
|
@ -0,0 +1,249 @@
|
|||
//===- LowerIntrinsics.cpp - Lower Intrinsics -------------------*- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the LowerIntrinsics pass. This pass processes FIRRTL
|
||||
// extmodules with intrinsic annotations and rewrites the instances as
|
||||
// appropriate.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "PassDetails.h"
|
||||
#include "circt/Dialect/FIRRTL/FIRRTLInstanceGraph.h"
|
||||
#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
|
||||
#include "circt/Dialect/FIRRTL/FIRRTLTypes.h"
|
||||
#include "circt/Dialect/FIRRTL/FIRRTLVisitors.h"
|
||||
#include "circt/Dialect/FIRRTL/Namespace.h"
|
||||
#include "circt/Dialect/FIRRTL/Passes.h"
|
||||
#include "mlir/IR/Diagnostics.h"
|
||||
#include "llvm/ADT/APSInt.h"
|
||||
#include "llvm/ADT/PostOrderIterator.h"
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
|
||||
using namespace circt;
|
||||
using namespace firrtl;
|
||||
|
||||
// Pass Infrastructure
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
namespace {
|
||||
struct LowerIntrinsicsPass : public LowerIntrinsicsBase<LowerIntrinsicsPass> {
|
||||
void runOnOperation() override;
|
||||
};
|
||||
} // end anonymous namespace
|
||||
|
||||
static ParseResult hasNPorts(StringRef name, FExtModuleOp mod, unsigned n) {
|
||||
if (mod.getPorts().size() != n) {
|
||||
mod.emitError(name) << " has " << mod.getPorts().size()
|
||||
<< " ports instead of " << n;
|
||||
return failure();
|
||||
}
|
||||
return success();
|
||||
}
|
||||
|
||||
static ParseResult namedPort(StringRef name, FExtModuleOp mod, unsigned n,
|
||||
StringRef portName) {
|
||||
auto ports = mod.getPorts();
|
||||
if (n >= ports.size()) {
|
||||
mod.emitError(name) << " missing port " << n;
|
||||
return failure();
|
||||
}
|
||||
if (!ports[n].getName().equals(portName)) {
|
||||
mod.emitError(name) << " port " << n << " named '" << ports[n].getName()
|
||||
<< "' instead of '" << portName << "'";
|
||||
return failure();
|
||||
}
|
||||
return success();
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
static ParseResult sizedPort(StringRef name, FExtModuleOp mod, unsigned n,
|
||||
int32_t size) {
|
||||
auto ports = mod.getPorts();
|
||||
if (n >= ports.size()) {
|
||||
mod.emitError(name) << " missing port " << n;
|
||||
return failure();
|
||||
}
|
||||
if (!ports[n].type.isa<T>()) {
|
||||
mod.emitError(name) << " port " << n << " not a correct type";
|
||||
return failure();
|
||||
}
|
||||
if (ports[n].type.cast<T>().getWidth() != size) {
|
||||
mod.emitError(name) << " port " << n << " not size " << size;
|
||||
return failure();
|
||||
}
|
||||
return success();
|
||||
}
|
||||
|
||||
static ParseResult hasNParam(StringRef name, FExtModuleOp mod, unsigned n) {
|
||||
unsigned num = 0;
|
||||
if (mod.getParameters())
|
||||
num = mod.getParameters().size();
|
||||
if (n != num) {
|
||||
mod.emitError(name) << " has " << num << " parameters instead of " << n;
|
||||
return failure();
|
||||
}
|
||||
return success();
|
||||
}
|
||||
static ParseResult namedParam(StringRef name, FExtModuleOp mod,
|
||||
StringRef paramName) {
|
||||
for (auto a : mod.getParameters()) {
|
||||
auto param = a.cast<ParamDeclAttr>();
|
||||
if (param.getName().getValue().equals(paramName)) {
|
||||
if (param.getValue().isa<StringAttr>())
|
||||
return success();
|
||||
|
||||
mod.emitError(name) << " test has parameter '" << param.getName()
|
||||
<< "' which should be a string but is not";
|
||||
return failure();
|
||||
}
|
||||
}
|
||||
mod.emitError(name) << " is missing parameter " << paramName;
|
||||
return failure();
|
||||
}
|
||||
|
||||
static bool lowerCirctSizeof(InstancePathCache &instancePathCache,
|
||||
FExtModuleOp mod) {
|
||||
auto ports = mod.getPorts();
|
||||
if (hasNPorts("circt.sizeof", mod, 2) ||
|
||||
namedPort("circt.sizeof", mod, 0, "i") ||
|
||||
namedPort("circt.sizeof", mod, 1, "size") ||
|
||||
sizedPort<UIntType>("circt.sizeof", mod, 1, 32) ||
|
||||
hasNParam("circt.sizeof", mod, 0))
|
||||
return false;
|
||||
|
||||
for (auto *use : instancePathCache.instanceGraph[mod]->uses()) {
|
||||
auto inst = cast<InstanceOp>(use->getInstance().getOperation());
|
||||
ImplicitLocOpBuilder builder(inst.getLoc(), inst);
|
||||
auto inputWire = builder.create<WireOp>(ports[0].type);
|
||||
inst.getResult(0).replaceAllUsesWith(inputWire);
|
||||
auto size = builder.create<SizeOfIntrinsicOp>(inputWire);
|
||||
inst.getResult(1).replaceAllUsesWith(size);
|
||||
inst.erase();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool lowerCirctIsX(InstancePathCache &instancePathCache,
|
||||
FExtModuleOp mod) {
|
||||
auto ports = mod.getPorts();
|
||||
if (hasNPorts("circt.isaX", mod, 2) || namedPort("circt.isX", mod, 0, "i") ||
|
||||
namedPort("circt.isX", mod, 1, "found") ||
|
||||
sizedPort<UIntType>("circt.isX", mod, 1, 1) ||
|
||||
hasNParam("circt.isX", mod, 0))
|
||||
return false;
|
||||
|
||||
for (auto *use : instancePathCache.instanceGraph[mod]->uses()) {
|
||||
auto inst = cast<InstanceOp>(use->getInstance().getOperation());
|
||||
ImplicitLocOpBuilder builder(inst.getLoc(), inst);
|
||||
auto inputWire = builder.create<WireOp>(ports[0].type);
|
||||
inst.getResult(0).replaceAllUsesWith(inputWire);
|
||||
auto size = builder.create<IsXIntrinsicOp>(inputWire);
|
||||
inst.getResult(1).replaceAllUsesWith(size);
|
||||
inst.erase();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool lowerCirctPlusArgTest(InstancePathCache &instancePathCache,
|
||||
FExtModuleOp mod) {
|
||||
if (hasNPorts("circt.plusargs.test", mod, 1) ||
|
||||
namedPort("circt.plusargs.test", mod, 0, "found") ||
|
||||
sizedPort<UIntType>("circt.plusargs.test", mod, 0, 1) ||
|
||||
hasNParam("circt.plusargs.test", mod, 1) ||
|
||||
namedParam("circt.plusargs.test", mod, "FORMAT"))
|
||||
return false;
|
||||
|
||||
auto param = mod.getParameters()[0].cast<ParamDeclAttr>();
|
||||
for (auto *use : instancePathCache.instanceGraph[mod]->uses()) {
|
||||
auto inst = cast<InstanceOp>(use->getInstance().getOperation());
|
||||
ImplicitLocOpBuilder builder(inst.getLoc(), inst);
|
||||
auto newop = builder.create<PlusArgsTestIntrinsicOp>(
|
||||
param.getValue().cast<StringAttr>());
|
||||
inst.getResult(0).replaceAllUsesWith(newop);
|
||||
inst.erase();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool lowerCirctPlusArgValue(InstancePathCache &instancePathCache,
|
||||
FExtModuleOp mod) {
|
||||
if (hasNPorts("circt.plusargs.value", mod, 2) ||
|
||||
namedPort("circt.plusargs.value", mod, 0, "found") ||
|
||||
namedPort("circt.plusargs.value", mod, 1, "result") ||
|
||||
sizedPort<UIntType>("circt.plusargs.value", mod, 0, 1) ||
|
||||
hasNParam("circt.plusargs.value", mod, 1) ||
|
||||
namedParam("circt.plusargs.value", mod, "FORMAT"))
|
||||
return false;
|
||||
|
||||
auto param = mod.getParameters()[0].cast<ParamDeclAttr>();
|
||||
|
||||
for (auto *use : instancePathCache.instanceGraph[mod]->uses()) {
|
||||
auto inst = cast<InstanceOp>(use->getInstance().getOperation());
|
||||
ImplicitLocOpBuilder builder(inst.getLoc(), inst);
|
||||
auto newop = builder.create<PlusArgsValueIntrinsicOp>(
|
||||
inst.getResultTypes(), param.getValue().cast<StringAttr>());
|
||||
inst.getResult(0).replaceAllUsesWith(newop.getFound());
|
||||
inst.getResult(1).replaceAllUsesWith(newop.getResult());
|
||||
inst.erase();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
std::pair<const char *, std::function<bool(InstancePathCache &, FExtModuleOp)>>
|
||||
intrinsics[] = {
|
||||
{"circt.sizeof", lowerCirctSizeof},
|
||||
{"circt.isX", lowerCirctIsX},
|
||||
{"circt.plusargs.test", lowerCirctPlusArgTest},
|
||||
{"circt.plusargs.value", lowerCirctPlusArgValue},
|
||||
};
|
||||
|
||||
// This is the main entrypoint for the lowering pass.
|
||||
void LowerIntrinsicsPass::runOnOperation() {
|
||||
size_t numFailures = 0;
|
||||
size_t numConverted = 0;
|
||||
InstancePathCache instancePathCache(getAnalysis<InstanceGraph>());
|
||||
for (auto op :
|
||||
llvm::make_early_inc_range(getOperation().getOps<FExtModuleOp>())) {
|
||||
auto anno = AnnotationSet(op).getAnnotation("circt.intrinsic");
|
||||
if (!anno)
|
||||
continue;
|
||||
auto intname = anno.getMember<StringAttr>("intrinsic");
|
||||
if (!intname) {
|
||||
op.emitError("Intrinsic annotation with no intrinsic name");
|
||||
++numFailures;
|
||||
continue;
|
||||
}
|
||||
bool found = false;
|
||||
for (const auto &intrinsic : intrinsics) {
|
||||
if (intname.getValue().equals(intrinsic.first)) {
|
||||
found = true;
|
||||
if (intrinsic.second(instancePathCache, op)) {
|
||||
++numConverted;
|
||||
op.erase();
|
||||
} else {
|
||||
++numFailures;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found) {
|
||||
op.emitError("Unknown intrinsic '") << intname << "'";
|
||||
++numFailures;
|
||||
}
|
||||
}
|
||||
if (numFailures)
|
||||
signalPassFailure();
|
||||
if (!numConverted)
|
||||
markAllAnalysesPreserved();
|
||||
}
|
||||
|
||||
/// This is the pass constructor.
|
||||
std::unique_ptr<mlir::Pass> circt::firrtl::createLowerIntrinsicsPass() {
|
||||
return std::make_unique<LowerIntrinsicsPass>();
|
||||
}
|
||||
|
|
@ -208,7 +208,7 @@ firrtl.circuit "Simple" attributes {annotations = [{class =
|
|||
%28 = firrtl.andr %18 : (!firrtl.uint<14>) -> !firrtl.uint<1>
|
||||
|
||||
// CHECK-NEXT: = comb.icmp bin ceq {{.*}}, %x_i1
|
||||
%x28 = firrtl.verif_isX %28 : !firrtl.uint<1>
|
||||
%x28 = firrtl.int.isX %28 : !firrtl.uint<1>
|
||||
|
||||
// CHECK-NEXT: [[XOREXT:%.+]] = comb.concat %c0_i11, [[XOR]]
|
||||
// CHECK-NEXT: [[SHIFT:%.+]] = comb.shru bin [[XOREXT]], [[VAL18]] : i14
|
||||
|
|
|
|||
|
|
@ -169,24 +169,6 @@ firrtl.circuit "padConstReg" {
|
|||
}
|
||||
}
|
||||
|
||||
// TODO: This requires SFCCompat
|
||||
// "pad zero when constant propping a register replaced with zero"
|
||||
firrtl.circuit "padZeroReg" {
|
||||
// CHECK-LABEL: firrtl.module @padZeroReg
|
||||
firrtl.module @padZeroReg(in %clock: !firrtl.clock, out %z: !firrtl.uint<16>) {
|
||||
%_r = firrtl.reg droppable_name %clock : !firrtl.uint<8>
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%0 = firrtl.or %_r, %c0_ui1 : (!firrtl.uint<8>, !firrtl.uint<1>) -> !firrtl.uint<8>
|
||||
firrtl.connect %_r, %0 : !firrtl.uint<8>, !firrtl.uint<8>
|
||||
%c171_ui8 = firrtl.constant 171 : !firrtl.uint<8>
|
||||
%_n = firrtl.node droppable_name %c171_ui8 : !firrtl.uint<8>
|
||||
%1 = firrtl.cat %_n, %_r : (!firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<16>
|
||||
firrtl.connect %z, %1 : !firrtl.uint<16>, !firrtl.uint<16>
|
||||
// _HECK: %[[TMP:.+]] = firrtl.constant 43776 : !firrtl.uint<16>
|
||||
// _HECK-NEXT: firrtl.strictconnect %z, %[[TMP]] : !firrtl.uint<16>
|
||||
}
|
||||
}
|
||||
|
||||
// should "pad constant connections to outputs when propagating"
|
||||
firrtl.circuit "padConstOut" {
|
||||
firrtl.module private @padConstOutChild(out %x: !firrtl.uint<8>) {
|
||||
|
|
|
|||
|
|
@ -2488,7 +2488,7 @@ firrtl.module @AnnotationsBlockRemoval(
|
|||
}
|
||||
|
||||
// CHECK-LABEL: firrtl.module @Verification
|
||||
firrtl.module @Verification(in %clock: !firrtl.clock, in %p: !firrtl.uint<1>) {
|
||||
firrtl.module @Verification(in %clock: !firrtl.clock, in %p: !firrtl.uint<1>, out %o : !firrtl.uint<1>) {
|
||||
%c0 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%c1 = firrtl.constant 1 : !firrtl.uint<1>
|
||||
|
||||
|
|
@ -2507,6 +2507,10 @@ firrtl.module @Verification(in %clock: !firrtl.clock, in %p: !firrtl.uint<1>) {
|
|||
firrtl.assume %clock, %c1, %p, "assume1"
|
||||
// CHECK-NOT: firrtl.cover
|
||||
firrtl.cover %clock, %c0, %p, "cover0"
|
||||
|
||||
// CHECK-NOT: firrtl.int.isX
|
||||
%x = firrtl.int.isX %c0 : !firrtl.uint<1>
|
||||
firrtl.strictconnect %o, %x : !firrtl.uint<1>
|
||||
}
|
||||
|
||||
// COMMON-LABEL: firrtl.module @MultibitMux
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-intrinsics))' %s | FileCheck %s
|
||||
|
||||
// CHECK-LABEL: "Foo"
|
||||
firrtl.circuit "Foo" {
|
||||
// CHECK-NOT: NameDoesNotMatter
|
||||
firrtl.extmodule @NameDoesNotMatter(in i : !firrtl.clock, out size : !firrtl.uint<32>) attributes
|
||||
{annotations = [{class = "circt.intrinsic", intrinsic = "circt.sizeof"}]}
|
||||
// CHECK-NOT: NameDoesNotMatter2
|
||||
firrtl.extmodule @NameDoesNotMatter2(in i : !firrtl.clock, out found : !firrtl.uint<1>) attributes
|
||||
{annotations = [{class = "circt.intrinsic", intrinsic = "circt.isX"}]}
|
||||
// CHECK-NOT: NameDoesNotMatter3
|
||||
firrtl.extmodule @NameDoesNotMatter3<FORMAT: none = "foo">(out found : !firrtl.uint<1>) attributes
|
||||
{annotations = [{class = "circt.intrinsic", intrinsic = "circt.plusargs.test"}]}
|
||||
// CHECK-NOT: NameDoesNotMatter4
|
||||
firrtl.extmodule @NameDoesNotMatter4<FORMAT: none = "foo">(out found : !firrtl.uint<1>, out result: !firrtl.uint<5>) attributes
|
||||
{annotations = [{class = "circt.intrinsic", intrinsic = "circt.plusargs.value"}]}
|
||||
|
||||
// CHECK: Foo
|
||||
firrtl.module @Foo(in %clk : !firrtl.clock) {
|
||||
%i1, %size = firrtl.instance "" @NameDoesNotMatter(in i : !firrtl.clock, out size : !firrtl.uint<32>)
|
||||
// CHECK-NOT: NameDoesNotMatter
|
||||
// CHECK: firrtl.int.sizeof
|
||||
firrtl.strictconnect %i1, %clk : !firrtl.clock
|
||||
|
||||
%i2, %found2 = firrtl.instance "" @NameDoesNotMatter2(in i : !firrtl.clock, out found : !firrtl.uint<1>)
|
||||
// CHECK-NOT: NameDoesNotMatter2
|
||||
// CHECK: firrtl.int.isX
|
||||
firrtl.strictconnect %i2, %clk : !firrtl.clock
|
||||
|
||||
%found3 = firrtl.instance "" @NameDoesNotMatter3(out found : !firrtl.uint<1>)
|
||||
// CHECK-NOT: NameDoesNotMatter3
|
||||
// CHECK: firrtl.int.plusargs.test "foo"
|
||||
|
||||
%found4, %result1 = firrtl.instance "" @NameDoesNotMatter4(out found : !firrtl.uint<1>, out result: !firrtl.uint<5>)
|
||||
// CHECK-NOT: NameDoesNotMatter4
|
||||
// CHECK: %5:2 = firrtl.int.plusargs.value "foo" : !firrtl.uint<5>
|
||||
}
|
||||
}
|
||||
|
|
@ -999,7 +999,7 @@ circuit MyModule : ; CHECK: firrtl.circuit "MyModule" {
|
|||
printf(clock, enable, "assertNotX:%d:value must not be X!", value)
|
||||
; CHECK: [[TMP1:%.+]] = firrtl.not %cond
|
||||
; CHECK: [[TMP2:%.+]] = firrtl.xorr %value
|
||||
; CHECK: [[TMP3:%.+]] = firrtl.verif_isX
|
||||
; CHECK: [[TMP3:%.+]] = firrtl.int.isX
|
||||
; CHECK: [[TMP4:%.+]] = firrtl.not
|
||||
; CHECK: [[TMP5:%.+]] = firrtl.or [[TMP1]], [[TMP4]]
|
||||
; CHECK: firrtl.assert %clock, [[TMP5]], %enable, "value must not be X!"
|
||||
|
|
|
|||
|
|
@ -612,6 +612,8 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
|
|||
return success();
|
||||
}
|
||||
|
||||
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerIntrinsicsPass());
|
||||
|
||||
// TODO: Move this to the O1 pipeline.
|
||||
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
|
||||
firrtl::createDropNamesPass(preserveMode));
|
||||
|
|
|
|||
Loading…
Reference in New Issue