[FIRRTL] Make GCT Sig. Map. a CircuitOp Pass, NFC

Change the Grand Central (GCT) Signal Mappings pass to be a pass that
operates on the whole FIRRTL circuit instead of on a module.  Continue
to keep its parallel execution behavior.  This is done in preparation
for modifications to the pass to support emission of a JSON structure
necessary for SiFive tooling which requires full-circuit information.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

include/circt/Dialect/FIRRTL/Passes.td

@@ -362,7 +362,7 @@ def GrandCentralTaps : Pass<"firrtl-grand-central-taps", "firrtl::CircuitOp"> {
 }
 
 def GrandCentralSignalMappings : Pass<"firrtl-grand-central-signal-mappings",
-                                      "FModuleOp"> {
+                                      "firrtl::CircuitOp"> {
   let summary = "Generate signal mappings that force/probe remote signals";
   let constructor = "circt::firrtl::createGrandCentralSignalMappingsPass()";
 }

lib/Dialect/FIRRTL/Transforms/GrandCentralSignalMappings.cpp

@@ -15,6 +15,7 @@
 #include "circt/Dialect/FIRRTL/Passes.h"
 #include "mlir/IR/ImplicitLocOpBuilder.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Parallel.h"
 
 #define DEBUG_TYPE "gct"
 
@@ -260,10 +261,23 @@ class GrandCentralSignalMappingsPass
 };
 
 void GrandCentralSignalMappingsPass::runOnOperation() {
-  FModuleOp module = getOperation();
+  CircuitOp circuit = getOperation();
-  ModuleSignalMappings mapper(module);
+
-  mapper.run();
+  auto processModule = [](FModuleOp module) -> bool {
-  if (mapper.allAnalysesPreserved)
+    ModuleSignalMappings mapper(module);
+    mapper.run();
+    return mapper.allAnalysesPreserved;
+  };
+
+  SmallVector<FModuleOp> modules(circuit.body().getOps<FModuleOp>());
+  // Note: this uses (unsigned)true instead of (bool)true for the reduction
+  // because llvm::parallelTransformReduce uses the "data" method of std::vector
+  // which is NOT provided for bool for optimization reasons.
+  bool allAnalysesPreserved = llvm::parallelTransformReduce(
+      modules.begin(), modules.end(), (unsigned)true,
+      [](bool acc, bool x) { return acc && x; }, processModule);
+
+  if (allAnalysesPreserved)
     markAllAnalysesPreserved();
 }
 

test/Dialect/FIRRTL/grand-central-signal-mappings.mlir

@@ -1,4 +1,4 @@
-// RUN: circt-opt --pass-pipeline='firrtl.circuit(firrtl.module(firrtl-grand-central-signal-mappings))' --split-input-file %s | FileCheck %s
+// RUN: circt-opt --pass-pipeline='firrtl.circuit(firrtl-grand-central-signal-mappings)' --split-input-file %s | FileCheck %s
 
 firrtl.circuit "SubCircuit" {
   firrtl.extmodule @FooExtern(in clockIn: !firrtl.clock, out clockOut: !firrtl.clock)

tools/firtool/firtool.cpp

@@ -500,8 +500,7 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
     auto &circuitPM = pm.nest<firrtl::CircuitOp>();
     circuitPM.addPass(firrtl::createGrandCentralPass());
     circuitPM.addPass(firrtl::createGrandCentralTapsPass());
-    circuitPM.nest<firrtl::FModuleOp>().addPass(
+    circuitPM.addPass(firrtl::createGrandCentralSignalMappingsPass());
-        firrtl::createGrandCentralSignalMappingsPass());
   }
 
   // Read black box source files into the IR.