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[HW] Move the WUW Enum into the hw namespace for consistency. 

The mechanism for this is a bit weird, see this bug for discussion:
https://bugs.llvm.org/show_bug.cgi?id=51932
This commit is contained in:
Chris Lattner 2021-09-21 17:35:14 -07:00
parent 2821d08959
commit 2ac86dd319
3 changed files with 22 additions and 19 deletions
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2
include/circt/Dialect/HW/HWAttributes.td
View File

@ -85,7 +85,9 @@ def ParamVerbatimAttr : AttrDef<HWDialect, "ParamVerbatim"> {
let mnemonic = "param.verbatim";
}
let cppNamespace = "circt::hw" in {
def WUW_Undefined : I32EnumAttrCase<"Undefined", 0>;
def WUW_PortOrder : I32EnumAttrCase<"PortOrder", 1>;
def WUWAttr : I32EnumAttr<"WUW", "Write Under Write Behavior",
[WUW_Undefined, WUW_PortOrder]>;
}

11
lib/Conversion/FIRRTLToHW/LowerToHW.cpp
View File

@ -182,7 +182,7 @@ struct FirMemory {
size_t readLatency;
size_t writeLatency;
size_t readUnderWrite;
WUW writeUnderWrite;
hw::WUW writeUnderWrite;
SmallVector<int32_t> writeClockIDs;
// Location is carried along but not considered part of the identity of this.
@ -279,9 +279,10 @@ static FirMemory analyzeMemOp(MemOp op) {
width = 0;
}
return {numReadPorts, numWritePorts, numReadWritePorts, (size_t)width,
op.depth(), op.readLatency(), op.writeLatency(), (size_t)op.ruw(),
WUW::PortOrder, writeClockIDs, op.getLoc()};
return {numReadPorts, numWritePorts, numReadWritePorts,
(size_t)width, op.depth(), op.readLatency(),
op.writeLatency(), (size_t)op.ruw(), hw::WUW::PortOrder,
writeClockIDs, op.getLoc()};
}
static SmallVector<FirMemory> collectFIRRTLMemories(FModuleOp module) {
@ -622,7 +623,7 @@ void FIRRTLModuleLowering::lowerMemoryDecls(ArrayRef<FirMemory> mems,
b.getNamedAttr("readUnderWrite",
b.getUI32IntegerAttr(mem.readUnderWrite)),
b.getNamedAttr("writeUnderWrite",
WUWAttr::get(b.getContext(), mem.writeUnderWrite)),
hw::WUWAttr::get(b.getContext(), mem.writeUnderWrite)),
b.getNamedAttr("writeClockIDs", b.getI32ArrayAttr(mem.writeClockIDs))};
// Make the global module for the memory

26
lib/Dialect/SV/Transforms/HWMemSimImpl.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/ADT/TypeSwitch.h"
using namespace circt;
using namespace hw;
//===----------------------------------------------------------------------===//
// HWMemSimImplPass Pass
@ -44,11 +45,11 @@ struct HWMemSimImplPass : public sv::HWMemSimImplBase<HWMemSimImplPass> {
void runOnOperation() override;
private:
void generateMemory(hw::HWModuleOp op, FirMemory mem);
void generateMemory(HWModuleOp op, FirMemory mem);
};
} // end anonymous namespace
static FirMemory analyzeMemOp(hw::HWModuleGeneratedOp op) {
static FirMemory analyzeMemOp(HWModuleGeneratedOp op) {
FirMemory mem;
mem.depth = op->getAttrOfType<IntegerAttr>("depth").getInt();
mem.numReadPorts = op->getAttrOfType<IntegerAttr>("numReadPorts").getUInt();
@ -86,13 +87,12 @@ static Value addPipelineStages(ImplicitLocOpBuilder &b, size_t stages,
return data;
}
void HWMemSimImplPass::generateMemory(hw::HWModuleOp op, FirMemory mem) {
void HWMemSimImplPass::generateMemory(HWModuleOp op, FirMemory mem) {
ImplicitLocOpBuilder b(UnknownLoc::get(&getContext()), op.getBody());
// Create a register for the memory.
auto dataType = b.getIntegerType(mem.dataWidth);
Value reg =
b.create<sv::RegOp>(hw::UnpackedArrayType::get(dataType, mem.depth),
Value reg = b.create<sv::RegOp>(UnpackedArrayType::get(dataType, mem.depth),
b.getStringAttr("Memory"));
SmallVector<Value, 4> outputs;
@ -139,7 +139,7 @@ void HWMemSimImplPass::generateMemory(hw::HWModuleOp op, FirMemory mem) {
Value rcond = b.createOrFold<comb::AndOp>(
en, b.createOrFold<comb::ICmpOp>(
comb::ICmpPredicate::eq, wmode,
b.createOrFold<hw::ConstantOp>(wmode.getType(), 0)));
b.createOrFold<ConstantOp>(wmode.getType(), 0)));
Value slot = b.create<sv::ArrayIndexInOutOp>(reg, addr);
Value x = b.create<sv::ConstantXOp>(dataType);
b.create<sv::AssignOp>(
@ -212,14 +212,14 @@ void HWMemSimImplPass::generateMemory(hw::HWModuleOp op, FirMemory mem) {
void HWMemSimImplPass::runOnOperation() {
auto topModule = getOperation().getBody();
SmallVector<hw::HWModuleGeneratedOp> toErase;
SmallVector<HWModuleGeneratedOp> toErase;
bool anythingChanged = false;
for (auto op : llvm::make_early_inc_range(
topModule->getOps<hw::HWModuleGeneratedOp>())) {
auto oldModule = cast<hw::HWModuleGeneratedOp>(op);
for (auto op :
llvm::make_early_inc_range(topModule->getOps<HWModuleGeneratedOp>())) {
auto oldModule = cast<HWModuleGeneratedOp>(op);
auto gen = oldModule.generatorKind();
auto genOp = cast<hw::HWGeneratorSchemaOp>(
auto genOp = cast<HWGeneratorSchemaOp>(
SymbolTable::lookupSymbolIn(getOperation(), gen));
if (genOp.descriptor() == "FIRRTL_Memory") {
@ -227,8 +227,8 @@ void HWMemSimImplPass::runOnOperation() {
OpBuilder builder(oldModule);
auto nameAttr = builder.getStringAttr(oldModule.getName());
auto newModule = builder.create<hw::HWModuleOp>(
oldModule.getLoc(), nameAttr, oldModule.getPorts());
auto newModule = builder.create<HWModuleOp>(oldModule.getLoc(), nameAttr,
oldModule.getPorts());
generateMemory(newModule, mem);
oldModule.erase();
anythingChanged = true;