[FIRRTL][LOA] Created Non-HW wires should always have droppable names. (#6101)

These will never appear in the output verilog, and may cause
the wires to be unnecessarily preserved.

cc #6099, addresses this for aggregates with non-hw in them.

lib/Dialect/FIRRTL/Transforms/LowerOpenAggs.cpp

@@ -636,13 +636,13 @@ LogicalResult Visitor::visitDecl(WireOp op) {
                             op.getForceable())
             .getResult();
 
-  // Create the non-HW wires.
+  // Create the non-HW wires.  Non-HW wire names are always droppable.
   for (auto &[type, fieldID, _, suffix] : mappings.fields)
     nonHWValues[FieldRef(op.getResult(), fieldID)] =
         builder
             .create<WireOp>(type,
                             builder.getStringAttr(Twine(op.getName()) + suffix),
-                            op.getNameKind())
+                            NameKindEnum::DroppableName)
             .getResult();
 
   for (auto fieldID : mappings.mapToNullInteriors)

test/Dialect/FIRRTL/lower-open-aggs.mlir

@@ -309,3 +309,18 @@ firrtl.circuit "WireSymbols" {
     %a = firrtl.wire sym [<@sym_a_c, 2, public>] : !firrtl.openbundle<b: string, c: uint<1>>
   }
 }
+
+// -----
+
+// Check that created wires for non-hw have droppable names.
+// Ensure name for hw-only portion preserves namekind.
+
+// CHECK-LABEL: circuit "NonHWWiresHaveDroppableNames"
+firrtl.circuit "NonHWWiresHaveDroppableNames" {
+  // CHECK-LABEL: module @NonHWWiresHaveDroppableNames
+  firrtl.module @NonHWWiresHaveDroppableNames() {
+    // CHECK:      %w = firrtl.wire interesting_name : !firrtl.bundle<a: uint<1>>
+    // CHECK-NEXT: %w_b = firrtl.wire : !firrtl.probe<uint<1>>
+    %w = firrtl.wire interesting_name : !firrtl.openbundle<a: uint<1>, b: probe<uint<1>>>
+  }
+}