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[firtool] Run CheckWidths pass, add option for InferWidths (#1036) 

* Run the `CheckWidths` pass when lowering to the RTL dialect to ensure
  there are no uninferred widths that will cause the lowering to fail.

* Add a `--infer-widths` option that runs the `InferWidths` pass.

Fixes #1032.
This commit is contained in:
Fabian Schuiki 2021-05-10 20:03:54 +02:00 committed by GitHub
parent de8c3827e8
commit 2891bdfadc
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1 changed files with 10 additions and 0 deletions
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10
tools/firtool/firtool.cpp
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@ -96,6 +96,11 @@ static cl::opt<bool>
cl::desc("ignore the @info locations in the .fir file"),
cl::init(false));
static cl::opt<bool>
inferWidths("infer-widths",
cl::desc("run the width inference pass on firrtl"),
cl::init(false));
enum OutputFormatKind {
OutputMLIR,
OutputVerilog,
@ -201,6 +206,9 @@ processBuffer(std::unique_ptr<llvm::MemoryBuffer> ownedBuffer,
// Allow optimizations to run multithreaded.
context.enableMultithreading(isMultithreaded);
if (inferWidths)
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidthsPass());
if (inliner)
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInlinerPass());
@ -213,6 +221,8 @@ processBuffer(std::unique_ptr<llvm::MemoryBuffer> ownedBuffer,
// Lower if we are going to verilog or if lowering was specifically requested.
if (lowerToRTL || outputFormat == OutputVerilog ||
outputFormat == OutputSplitVerilog) {
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
firrtl::createCheckWidthsPass());
pm.addPass(createLowerFIRRTLToRTLPass());
pm.addPass(sv::createRTLMemSimImplPass());