mirror of https://github.com/llvm/circt.git
[FIRRTL] GCT Views: Verilator Integration Test, NFC (#1778)
Add an integration test of Grand Central Views that uses Verilator to
lint and type-check the produced SystemVerilog output. This is
primarily done to test the following features:
- All necessary interfaces are generated
- All XMRs are valid (XMRs use the correct instance names)
Both single file ("firtool -verilog") and multi-file output ("firtool
-split-verilog" with an annotation file doing extraction) are tested.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This commit is contained in:
Schuyler Eldridge
GitHub
parent
c6b93aa292
commit
21f713689b
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; RUN: rm -rf %t && mkdir %t && firtool --firrtl-grand-central --split-verilog --annotation-file %s.anno.json --annotation-file %s.extract.anno.json -o %t %s && cd %t && verilator --sv --lint-only Top.sv bindings.sv
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; RUN: firtool --firrtl-grand-central --verilog --annotation-file %s.anno.json %s > %t.one-file.sv && verilator --sv --lint-only %t.one-file.sv
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; REQUIRES: verilator
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circuit Top :
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module Submodule :
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input clock : Clock
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input reset : Reset
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input in : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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output out : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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wire w : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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w.otherOther.other.sint <= in.otherOther.other.sint
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w.otherOther.other.uint <= in.otherOther.other.uint
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w.vecOfBundle[0].sint <= in.vecOfBundle[0].sint
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w.vecOfBundle[0].uint <= in.vecOfBundle[0].uint
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w.vecOfBundle[1].sint <= in.vecOfBundle[1].sint
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w.vecOfBundle[1].uint <= in.vecOfBundle[1].uint
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w.vec[0] <= in.vec[0]
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w.vec[1] <= in.vec[1]
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w.uint <= in.uint
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out.otherOther.other.sint <= w.otherOther.other.sint
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out.otherOther.other.uint <= w.otherOther.other.uint
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out.vecOfBundle[0].sint <= w.vecOfBundle[0].sint
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out.vecOfBundle[0].uint <= w.vecOfBundle[0].uint
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out.vecOfBundle[1].sint <= w.vecOfBundle[1].sint
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out.vecOfBundle[1].uint <= w.vecOfBundle[1].uint
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out.vec[0] <= w.vec[0]
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out.vec[1] <= w.vec[1]
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out.uint <= w.uint
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module MyView_companion :
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output io : { }
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wire _WIRE : UInt<1>
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_WIRE <= UInt<1>("h0")
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module DUT :
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input clock : Clock
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input reset : Reset
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input in : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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output out : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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wire w : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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inst submodule of Submodule
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submodule.clock <= clock
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submodule.reset <= reset
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w.otherOther.other.sint <= in.otherOther.other.sint
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w.otherOther.other.uint <= in.otherOther.other.uint
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w.vecOfBundle[0].sint <= in.vecOfBundle[0].sint
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w.vecOfBundle[0].uint <= in.vecOfBundle[0].uint
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w.vecOfBundle[1].sint <= in.vecOfBundle[1].sint
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w.vecOfBundle[1].uint <= in.vecOfBundle[1].uint
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w.vec[0] <= in.vec[0]
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w.vec[1] <= in.vec[1]
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w.uint <= in.uint
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submodule.in.otherOther.other.sint <= w.otherOther.other.sint
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submodule.in.otherOther.other.uint <= w.otherOther.other.uint
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submodule.in.vecOfBundle[0].sint <= w.vecOfBundle[0].sint
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submodule.in.vecOfBundle[0].uint <= w.vecOfBundle[0].uint
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submodule.in.vecOfBundle[1].sint <= w.vecOfBundle[1].sint
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submodule.in.vecOfBundle[1].uint <= w.vecOfBundle[1].uint
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submodule.in.vec[0] <= w.vec[0]
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submodule.in.vec[1] <= w.vec[1]
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submodule.in.uint <= w.uint
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out.otherOther.other.sint <= submodule.out.otherOther.other.sint
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out.otherOther.other.uint <= submodule.out.otherOther.other.uint
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out.vecOfBundle[0].sint <= submodule.out.vecOfBundle[0].sint
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out.vecOfBundle[0].uint <= submodule.out.vecOfBundle[0].uint
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out.vecOfBundle[1].sint <= submodule.out.vecOfBundle[1].sint
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out.vecOfBundle[1].uint <= submodule.out.vecOfBundle[1].uint
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out.vec[0] <= submodule.out.vec[0]
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out.vec[1] <= submodule.out.vec[1]
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out.uint <= submodule.out.uint
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inst MyView_companion of MyView_companion
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module Top :
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input clock : Clock
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input reset : UInt<1>
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input in : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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output out : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}
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inst dut of DUT
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dut.clock <= clock
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dut.reset <= reset
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dut.in.otherOther.other.sint <= in.otherOther.other.sint
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dut.in.otherOther.other.uint <= in.otherOther.other.uint
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dut.in.vecOfBundle[0].sint <= in.vecOfBundle[0].sint
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dut.in.vecOfBundle[0].uint <= in.vecOfBundle[0].uint
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dut.in.vecOfBundle[1].sint <= in.vecOfBundle[1].sint
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dut.in.vecOfBundle[1].uint <= in.vecOfBundle[1].uint
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dut.in.vec[0] <= in.vec[0]
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dut.in.vec[1] <= in.vec[1]
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dut.in.uint <= in.uint
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out.otherOther.other.sint <= dut.out.otherOther.other.sint
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out.otherOther.other.uint <= dut.out.otherOther.other.uint
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out.vecOfBundle[0].sint <= dut.out.vecOfBundle[0].sint
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out.vecOfBundle[0].uint <= dut.out.vecOfBundle[0].uint
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out.vecOfBundle[1].sint <= dut.out.vecOfBundle[1].sint
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out.vecOfBundle[1].uint <= dut.out.vecOfBundle[1].uint
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out.vec[0] <= dut.out.vec[0]
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out.vec[1] <= dut.out.vec[1]
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out.uint <= dut.out.uint
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@ -0,0 +1,515 @@
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[
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{
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"class": "sifive.enterprise.grandcentral.ViewAnnotation",
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"name": "MyView",
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"companion": "~Top|MyView_companion",
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"parent": "~Top|DUT",
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"view": {
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "MyInterface",
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"elements": [
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{
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"name": "uint",
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"description": "a wire called 'uint'",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "uint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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},
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{
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"name": "vec",
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"description": "a vector called 'vec'",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedVectorType",
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"elements": [
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{
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vec"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 0
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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},
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{
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vec"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 1
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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]
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}
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},
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{
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"name": "vecOfBundle",
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"description": "a vector of a bundle",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedVectorType",
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"elements": [
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{
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "VecOfBundle",
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"elements": [
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{
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"name": "sint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vecOfBundle"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 0
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "sint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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},
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{
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"name": "uint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vecOfBundle"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 0
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "uint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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}
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]
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},
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{
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "VecOfBundle",
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"elements": [
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{
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"name": "sint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vecOfBundle"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 1
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "sint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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},
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{
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"name": "uint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vecOfBundle"
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},
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{
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"class": "firrtl.annotations.TargetToken$Index",
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"value": 1
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "uint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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}
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]
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}
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]
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}
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},
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{
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"name": "otherOther",
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"description": "another bundle",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "OtherOther",
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"elements": [
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{
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"name": "other",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
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"defName": "Other",
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"elements": [
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{
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"name": "sint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "otherOther"
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "other"
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "sint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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},
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{
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"name": "uint",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "DUT",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "otherOther"
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "other"
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},
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "uint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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}
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]
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}
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}
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]
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}
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},
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{
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"name": "sub_uint",
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"description": "a wire called 'uint' in the submodule",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "Submodule",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "uint"
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}
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]
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},
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"tpe": {
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"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
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}
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}
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},
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{
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"name": "sub_vec",
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"description": "a vector called 'vec' in the submodule",
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"tpe": {
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"class": "sifive.enterprise.grandcentral.AugmentedVectorType",
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"elements": [
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{
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"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
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"ref": {
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"circuit": "Top",
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"module": "Submodule",
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"path": [],
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"ref": "w",
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"component": [
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{
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"class": "firrtl.annotations.TargetToken$Field",
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"value": "vec"
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},
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{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 0
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
},
|
||||
{
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
|
||||
"ref": {
|
||||
"circuit": "Top",
|
||||
"module": "Submodule",
|
||||
"path": [],
|
||||
"ref": "w",
|
||||
"component": [
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "vec"
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 1
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "sub_vecOfBundle",
|
||||
"description": "a vector of a bundle in the submodule with a\nmultiline comment",
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedVectorType",
|
||||
"elements": [
|
||||
{
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
|
||||
"defName": "Sub_vecOfBundle",
|
||||
"elements": [
|
||||
{
|
||||
"name": "sint",
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
|
||||
"ref": {
|
||||
"circuit": "Top",
|
||||
"module": "Submodule",
|
||||
"path": [],
|
||||
"ref": "w",
|
||||
"component": [
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "vecOfBundle"
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 0
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "sint"
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "uint",
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
|
||||
"ref": {
|
||||
"circuit": "Top",
|
||||
"module": "Submodule",
|
||||
"path": [],
|
||||
"ref": "w",
|
||||
"component": [
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "vecOfBundle"
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 0
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "uint"
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedBundleType",
|
||||
"defName": "Sub_vecOfBundle",
|
||||
"elements": [
|
||||
{
|
||||
"name": "sint",
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
|
||||
"ref": {
|
||||
"circuit": "Top",
|
||||
"module": "Submodule",
|
||||
"path": [],
|
||||
"ref": "w",
|
||||
"component": [
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "vecOfBundle"
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 1
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "sint"
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "uint",
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.AugmentedGroundType",
|
||||
"ref": {
|
||||
"circuit": "Top",
|
||||
"module": "Submodule",
|
||||
"path": [],
|
||||
"ref": "w",
|
||||
"component": [
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "vecOfBundle"
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Index",
|
||||
"value": 1
|
||||
},
|
||||
{
|
||||
"class": "firrtl.annotations.TargetToken$Field",
|
||||
"value": "uint"
|
||||
}
|
||||
]
|
||||
},
|
||||
"tpe": {
|
||||
"class": "sifive.enterprise.grandcentral.GrandCentralView$UnknownGroundType$"
|
||||
}
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
[
|
||||
{
|
||||
"class":"sifive.enterprise.grandcentral.ExtractGrandCentralAnnotation",
|
||||
"directory":"",
|
||||
"filename":"bindings.sv"
|
||||
}
|
||||
]
|
||||
Loading…
Reference in New Issue