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[FIRRTL] Replaced 'replicate' to correctly named 'replace' flags (#7442) 

Renamed and replaced shouldReplicateSequentialMemories to shouldReplaceSequentialMemories per issue #7384
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jpien13 2024-08-06 17:47:47 -04:00 committed by GitHub
parent 1645d71c1d
commit 1a8f82e7a6
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2 changed files with 5 additions and 5 deletions
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2
include/circt/Firtool/Firtool.h
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@ -96,7 +96,7 @@ public:
return allowAddingPortsOnPublic; return allowAddingPortsOnPublic;
} }
bool shouldConvertProbesToSignals() const { return probesToSignals; } bool shouldConvertProbesToSignals() const { return probesToSignals; }
bool shouldReplicateSequentialMemories() const { return replSeqMem; } bool shouldReplaceSequentialMemories() const { return replSeqMem; }
bool shouldDisableOptimization() const { return disableOptimization; } bool shouldDisableOptimization() const { return disableOptimization; }
bool shouldLowerMemories() const { return lowerMemories; } bool shouldLowerMemories() const { return lowerMemories; }
bool shouldDedup() const { return !noDedup; } bool shouldDedup() const { return !noDedup; }

8
lib/Firtool/Firtool.cpp
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@ -78,7 +78,7 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidthsPass()); pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferWidthsPass());
pm.nest<firrtl::CircuitOp>().addPass( pm.nest<firrtl::CircuitOp>().addPass(
firrtl::createMemToRegOfVecPass(opt.shouldReplicateSequentialMemories(), firrtl::createMemToRegOfVecPass(opt.shouldReplaceSequentialMemories(),
opt.shouldIgnoreReadEnableMemories())); opt.shouldIgnoreReadEnableMemories()));
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResetsPass()); pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInferResetsPass());
@ -161,7 +161,7 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass( pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
firrtl::createInferReadWritePass()); firrtl::createInferReadWritePass());
if (opt.shouldReplicateSequentialMemories()) if (opt.shouldReplaceSequentialMemories())
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemoryPass()); pm.nest<firrtl::CircuitOp>().addPass(firrtl::createLowerMemoryPass());
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createPrefixModulesPass()); pm.nest<firrtl::CircuitOp>().addPass(firrtl::createPrefixModulesPass());
@ -176,7 +176,7 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPortsPass()); pm.addNestedPass<firrtl::CircuitOp>(firrtl::createAddSeqMemPortsPass());
pm.addPass(firrtl::createCreateSiFiveMetadataPass( pm.addPass(firrtl::createCreateSiFiveMetadataPass(
opt.shouldReplicateSequentialMemories(), opt.shouldReplaceSequentialMemories(),
opt.getReplaceSequentialMemoriesFile())); opt.getReplaceSequentialMemoriesFile()));
pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstancesPass()); pm.addNestedPass<firrtl::CircuitOp>(firrtl::createExtractInstancesPass());
@ -303,7 +303,7 @@ LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
FirtoolOptions::RandomKind::Mem), FirtoolOptions::RandomKind::Mem),
/*disableRegRandomization=*/ /*disableRegRandomization=*/
!opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg), !opt.isRandomEnabled(FirtoolOptions::RandomKind::Reg),
/*replSeqMem=*/opt.shouldReplicateSequentialMemories(), /*replSeqMem=*/opt.shouldReplaceSequentialMemories(),
/*readEnableMode=*/opt.shouldIgnoreReadEnableMemories() /*readEnableMode=*/opt.shouldIgnoreReadEnableMemories()
? seq::ReadEnableMode::Ignore ? seq::ReadEnableMode::Ignore
: seq::ReadEnableMode::Undefined, : seq::ReadEnableMode::Undefined,