make firtool output options and pipeline structure a bit more sensible (#2358)

make firtool output options and pipeline structure a bit more sensible

integration_test/EmitVerilog/exampleCodeGen.fir

@@ -1,5 +1,5 @@
 ; REQUIRES: verilator
-; RUN: firtool -verilog -lower-to-hw %s > %t.sv
+; RUN: firtool -verilog %s > %t.sv
 ; RUN: circt-rtl-sim.py %t.sv 2>&1 | tee %t.out
 ; RUN: grep PASS %t.out
 

integration_test/EmitVerilog/standards-verilator.mlir

@@ -1,12 +1,12 @@
 // REQUIRES: verilator
 
-// RUN: firtool --lower-to-hw --verilog %s > %t1.1995.v
+// RUN: firtool --verilog %s > %t1.1995.v
-// RUN: firtool --lower-to-hw --verilog %s > %t1.2001.v
+// RUN: firtool --verilog %s > %t1.2001.v
-// RUN: firtool --lower-to-hw --verilog %s > %t1.2005.v
+// RUN: firtool --verilog %s > %t1.2005.v
-// RUN: firtool --lower-to-hw --verilog %s > %t1.2005.sv
+// RUN: firtool --verilog %s > %t1.2005.sv
-// RUN: firtool --lower-to-hw --verilog %s > %t1.2009.sv
+// RUN: firtool --verilog %s > %t1.2009.sv
-// RUN: firtool --lower-to-hw --verilog %s > %t1.2012.sv
+// RUN: firtool --verilog %s > %t1.2012.sv
-// RUN: firtool --lower-to-hw --verilog %s> %t1.2017.sv
+// RUN: firtool --verilog %s> %t1.2017.sv
 
 // RUN: verilator --lint-only +1364-1995ext+v %t1.1995.v || true
 // RUN: verilator --lint-only +1364-2001ext+v %t1.2001.v || true

integration_test/EmitVerilog/verilog_equiv.fir

@@ -1,8 +1,8 @@
 ; REQUIRES: yosys
 ; RUN: split-file %s %t
-; RUN: firtool %t/test_mod.fir --format=fir --lower-to-hw -verilog -o %t/test_mod.fir.v
+; RUN: firtool %t/test_mod.fir --format=fir -verilog -o %t/test_mod.fir.v
-; RUN: firtool %t/test_unary.fir --format=fir --lower-to-hw -verilog -o %t/test_unary.fir.v
+; RUN: firtool %t/test_unary.fir --format=fir -verilog -o %t/test_unary.fir.v
-; RUN: firtool %t/test_prim.fir --format=fir --lower-to-hw -verilog -o %t/test_prim.fir.v
+; RUN: firtool %t/test_prim.fir --format=fir -verilog -o %t/test_prim.fir.v
 ; RUN: equiv-rtl.sh %t/test_mod.fir.v %t/test_mod.v test_mod
 ; RUN: equiv-rtl.sh %t/test_unary.fir.v %t/test_unary.v test_unary
 ; RUN: equiv-rtl.sh %t/test_prim.fir.v %t/test_prim.v test_prim

test/Dialect/FIRRTL/SFCTests/async-reset-errors.mlir

@@ -1,4 +1,4 @@
-// RUN: firtool --lower-to-hw --split-input-file --verify-diagnostics %s
+// RUN: firtool --hw --split-input-file --verify-diagnostics %s
 // These will be picked up by https://github.com/llvm/circt/pull/1444
 
 // Tests extracted from:

test/Dialect/FIRRTL/SFCTests/async-reset.fir

@@ -1,4 +1,4 @@
-; RUN: firtool --split-input-file %s | FileCheck %s
+; RUN: firtool --split-input-file %s --ir-fir | FileCheck %s
 ; Tests extracted from:
 ; - test/scala/firrtlTests/AsyncResetSpec.scala
 

test/Dialect/FIRRTL/SFCTests/async-reset.mlir

@@ -1,4 +1,4 @@
-// RUN: firtool %s | FileCheck %s
+// RUN: firtool --ir-fir %s | FileCheck %s
 // Tests extracted from:
 // - test/scala/firrtlTests/AsyncResetSpec.scala
 

test/Dialect/FIRRTL/SFCTests/remove-reset.fir

@@ -1,4 +1,4 @@
-; RUN: firtool --split-input-file %s | FileCheck %s
+; RUN: firtool --split-input-file %s --ir-fir | FileCheck %s
 ; Tests extracted from:
 ; - test/scala/firrtlTests/transforms/RemoveResetSpec.scala
 

test/Dialect/FIRRTL/SFCTests/width-spec.fir

@@ -1,4 +1,4 @@
-; RUN: firtool --split-input-file %s | FileCheck %s
+; RUN: firtool --split-input-file %s --ir-fir | FileCheck %s
 ; Tests extracted from:
 ; - test/scala/firrtlTests/WidthSpec.scala
 

test/firtool/blackbox.mlir

@@ -1,5 +1,5 @@
 // RUN: rm -rf %t
-// RUN: firtool %s --blackbox-resource-path=%S/.. | firtool --format=mlir --split-verilog -o=%t --blackbox-path=%S --blackbox-resource-path=%S/..
+// RUN: firtool %s --ir-fir --blackbox-resource-path=%S/.. | firtool --format=mlir --split-verilog -o=%t --blackbox-path=%S --blackbox-resource-path=%S/..
 // RUN: FileCheck %s --check-prefix=VERILOG-TOP < %t/test_mod.sv
 // RUN: FileCheck %s --check-prefix=VERILOG-FOO < %t/magic/blackbox-inline.v
 // RUN: FileCheck %s --check-prefix=VERILOG-HDR < %t/magic/blackbox-inline.svh

test/firtool/firtool.fir

@@ -1,12 +1,12 @@
-; RUN: firtool %s --format=fir -mlir    | circt-opt | FileCheck %s --check-prefix=MLIR
+; RUN: firtool %s --format=fir --ir-fir    | circt-opt | FileCheck %s --check-prefix=MLIR
-; RUN: firtool %s --format=fir -mlir --annotation-file %s.anno.json,%s.anno.1.json | circt-opt | FileCheck %s --check-prefix=ANNOTATIONS
+; RUN: firtool %s --format=fir --ir-fir --annotation-file %s.anno.json,%s.anno.1.json | circt-opt | FileCheck %s --check-prefix=ANNOTATIONS
-; RUN: firtool %s --format=fir -mlir --annotation-file %s.anno.json --annotation-file %s.anno.1.json | circt-opt | FileCheck %s --check-prefix=ANNOTATIONS
+; RUN: firtool %s --format=fir --ir-fir --annotation-file %s.anno.json --annotation-file %s.anno.1.json | circt-opt | FileCheck %s --check-prefix=ANNOTATIONS
-; RUN: firtool %s --format=fir -mlir -lower-to-hw | circt-opt | FileCheck %s --check-prefix=MLIRLOWER
+; RUN: firtool %s --format=fir --ir-hw | circt-opt | FileCheck %s --check-prefix=MLIRLOWER
 ; RUN: firtool %s --format=fir -verilog |             FileCheck %s --check-prefix=VERILOG
-; RUN: firtool %s --annotation-file %s.anno.json,%s.anno.1.json --mlir --parse-only | FileCheck %s --check-prefix=ANNOTATIONS
+; RUN: firtool %s --annotation-file %s.anno.json,%s.anno.1.json --parse-only | FileCheck %s --check-prefix=ANNOTATIONS
 ; RUN: firtool %s --omir-file %s.omir.anno.json --parse-only | FileCheck %s --check-prefix=OMIR
 ; RUN: firtool %s --omir-file %s.omir.anno.json --output-omir meta.omir.json --verilog | FileCheck %s --check-prefix=OMIROUT
-; RUN: firtool %s --format=fir -verilog-ir | circt-opt | FileCheck %s --check-prefix=VERILOG-IR
+; RUN: firtool %s --format=fir --ir-verilog | circt-opt | FileCheck %s --check-prefix=VERILOG-IR
 
 
 circuit test_mod : %[[{"a": "a"}]]

test/firtool/firtool.mlir

@@ -1,4 +1,4 @@
-// RUN: firtool %s --format=mlir -mlir    | circt-opt | FileCheck %s --check-prefix=MLIR
+// RUN: firtool %s --format=mlir --ir-fir    | circt-opt | FileCheck %s --check-prefix=MLIR
 // RUN: firtool %s --format=mlir -verilog |           FileCheck %s --check-prefix=VERILOG
 
 firrtl.circuit "Top" {

test/firtool/memory.fir

@@ -1,5 +1,5 @@
-; RUN: firtool %s --format=fir  --lower-to-hw | FileCheck %s 
+; RUN: firtool %s --format=fir  --ir-hw | FileCheck %s 
-; RUN: firtool %s --format=fir  --lower-to-hw --ignore-read-enable-mem | FileCheck --check-prefix=READ %s 
+; RUN: firtool %s --format=fir  --ir-hw --ignore-read-enable-mem | FileCheck --check-prefix=READ %s 
 
 circuit Qux:
   module Qux:

test/firtool/optimizations.fir

@@ -1,5 +1,5 @@
-; RUN: firtool %s --format=fir              | circt-opt | FileCheck %s --check-prefix=OPT
+; RUN: firtool %s --format=fir --ir-fir              | circt-opt | FileCheck %s --check-prefix=OPT
-; RUN: firtool %s --format=fir -disable-opt | circt-opt | FileCheck %s --check-prefix=NOOPT
+; RUN: firtool %s --format=fir --ir-fir -disable-opt | circt-opt | FileCheck %s --check-prefix=NOOPT
 
 circuit test_cse :
   module test_cse :

test/firtool/phase-ordering.fir

@@ -1,4 +1,4 @@
-; RUN: firtool %s --format=fir | FileCheck %s
+; RUN: firtool %s --format=fir --ir-fir | FileCheck %s
 
 ; Temporary wires should not be introduced by type lowering, and if they are,
 ; they should be cleaned up by canonicalize.

test/firtool/style.fir

@@ -1,6 +1,6 @@
-; RUN: firtool %s | FileCheck %s --check-prefix=DEFAULT
+; RUN: firtool %s --ir-fir| FileCheck %s --check-prefix=DEFAULT
-; RUN: not firtool --lowering-options=bad-option %s 2>&1 | FileCheck %s --check-prefix=BADOPTION
+; RUN: not firtool --ir-fir --lowering-options=bad-option %s 2>&1 | FileCheck %s --check-prefix=BADOPTION
-; RUN: firtool --lowering-options=noAlwaysComb %s | FileCheck %s --check-prefix=OPTIONS
+; RUN: firtool --ir-fir --lowering-options=noAlwaysComb %s | FileCheck %s --check-prefix=OPTIONS
 
 circuit test :
   module test :

tools/firtool/firtool.cpp

@@ -67,10 +67,6 @@ static cl::opt<std::string>
                    cl::desc("Output filename, or directory for split output"),
                    cl::value_desc("filename"), cl::init("-"));
 
-static cl::opt<bool>
-    parseOnly("parse-only",
-              cl::desc("Stop after parsing inputs and annotations"));
-
 static cl::opt<bool>
     splitInputFile("split-input-file",
                    cl::desc("Split the input file into pieces and process each "
@@ -90,9 +86,6 @@ static cl::opt<bool> inliner("inline",
                              cl::desc("Run the FIRRTL module inliner"),
                              cl::init(true));
 
-static cl::opt<bool> lowerToHW("lower-to-hw",
-                               cl::desc("run the lower-to-hw pass"));
-
 static cl::opt<bool> enableAnnotationWarning(
     "warn-on-unprocessed-annotations",
     cl::desc("Warn about annotations that were not removed by lower-to-hw"),
@@ -205,25 +198,30 @@ static cl::opt<bool> newAnno("new-anno",
                              cl::init(false));
 
 enum OutputFormatKind {
-  OutputMLIR,
+  OutputParseOnly,
+  OutputIRFir,
+  OutputIRHW,
+  OutputIRVerilog,
   OutputVerilog,
   OutputSplitVerilog,
-  OutputVerilogIR,
   OutputDisabled
 };
 
 static cl::opt<OutputFormatKind> outputFormat(
     cl::desc("Specify output format:"),
-    cl::values(clEnumValN(OutputMLIR, "mlir", "Emit MLIR dialect"),
+    cl::values(
-               clEnumValN(OutputVerilog, "verilog", "Emit Verilog"),
+        clEnumValN(OutputParseOnly, "parse-only",
-               clEnumValN(OutputSplitVerilog, "split-verilog",
+                   "Emit FIR dialect after parsing"),
-                          "Emit Verilog (one file per module; specify "
+        clEnumValN(OutputIRFir, "ir-fir", "Emit FIR dialect after pipeline"),
-                          "directory with -o=<dir>)"),
+        clEnumValN(OutputIRHW, "ir-hw", "Emit HW dialect"),
-               clEnumValN(OutputVerilogIR, "verilog-ir",
+        clEnumValN(OutputIRVerilog, "ir-verilog",
-                          "Emit IR after Verilog lowering"),
+                   "Emit IR after Verilog lowering"),
-               clEnumValN(OutputDisabled, "disable-output",
+        clEnumValN(OutputVerilog, "verilog", "Emit Verilog"),
-                          "Do not output anything")),
+        clEnumValN(OutputSplitVerilog, "split-verilog",
-    cl::init(OutputMLIR));
+                   "Emit Verilog (one file per module; specify "
+                   "directory with -o=<dir>)"),
+        clEnumValN(OutputDisabled, "disable-output", "Do not output anything")),
+    cl::init(OutputVerilog));
 
 static cl::opt<bool>
     verifyPasses("verify-each",
@@ -308,23 +306,11 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
     return failure();
 
   // If the user asked for just a parse, stop here.
-  if (parseOnly) {
+  if (outputFormat == OutputParseOnly) {
     mlir::ModuleOp theModule = module.release();
-    switch (outputFormat) {
+    auto outputTimer = ts.nest("Print .mlir output");
-    case OutputMLIR: {
+    theModule->print(outputFile.getValue()->os());
-      auto outputTimer = ts.nest("Print .mlir output");
+    return success();
-      theModule->print(outputFile.getValue()->os());
-      return success();
-    }
-    case OutputDisabled:
-      return success();
-    case OutputVerilog:
-    case OutputSplitVerilog:
-    case OutputVerilogIR:
-      llvm::errs()
-          << "verilog emission is not supported in -parse-only mode.\n";
-      return failure();
-    }
   }
 
   // Apply any pass manager command line options.
@@ -423,8 +409,7 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
         firrtl::createEmitOMIRPass(omirOutFile));
 
   // Lower if we are going to verilog or if lowering was specifically requested.
-  if (lowerToHW || outputFormat == OutputVerilog ||
+  if (outputFormat != OutputIRFir) {
-      outputFormat == OutputSplitVerilog || outputFormat == OutputVerilogIR) {
     pm.addPass(createLowerFIRRTLToHWPass(enableAnnotationWarning.getValue(),
                                          nonConstAsyncResetValueIsError));
     pm.addPass(sv::createHWMemSimImplPass(replSeqMem, ignoreReadEnableMem));
@@ -443,7 +428,7 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
 
   // Add passes specific to Verilog emission if we're going there.
   if (outputFormat == OutputVerilog || outputFormat == OutputSplitVerilog ||
-      outputFormat == OutputVerilogIR) {
+      outputFormat == OutputIRVerilog) {
     // Legalize unsupported operations within the modules.
     pm.nest<hw::HWModuleOp>().addPass(sv::createHWLegalizeModulesPass());
 
@@ -455,8 +440,7 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
 
     // Emit a single file or multiple files depending on the output format.
     switch (outputFormat) {
-    case OutputMLIR:
+    default:
-    case OutputDisabled:
       llvm_unreachable("can't reach this");
     case OutputVerilog:
       pm.addPass(createExportVerilogPass(outputFile.getValue()->os()));
@@ -464,7 +448,7 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
     case OutputSplitVerilog:
       pm.addPass(createExportSplitVerilogPass(outputFilename));
       break;
-    case OutputVerilogIR:
+    case OutputIRVerilog:
       // Run the ExportVerilog pass to get its lowering, but discard the output.
       pm.addPass(createExportVerilogPass(llvm::nulls()));
       break;
@@ -483,7 +467,8 @@ processBuffer(MLIRContext &context, TimingScope &ts, llvm::SourceMgr &sourceMgr,
   if (failed(pm.run(module.get())))
     return failure();
 
-  if (outputFormat == OutputMLIR || outputFormat == OutputVerilogIR) {
+  if (outputFormat == OutputIRFir || outputFormat == OutputIRHW ||
+      outputFormat == OutputIRVerilog) {
     auto outputTimer = ts.nest("Print .mlir output");
     module->print(outputFile.getValue()->os());
   }