mirror of https://github.com/llvm/circt.git
[ExportVerilog] Pull parameter expr printing into ModuleEmitter, NFC.
This gives parameter expresion printing access to the current module, as well as the GlobalNameTable.
This commit is contained in:
Chris Lattner
parent
7df98af7c7
commit
061a0f300f
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@ -94,163 +94,6 @@ struct SubExprInfo {
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// Helper routines
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//===----------------------------------------------------------------------===//
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/// Helper that prints a parameter constant value in a Verilog compatible way.
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/// This returns the precedence of the generated string.
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static SubExprInfo
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printParamValue(Attribute value, raw_ostream &os,
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VerilogPrecedence parenthesizeIfLooserThan,
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function_ref<InFlightDiagnostic()> emitError) {
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if (auto intAttr = value.dyn_cast<IntegerAttr>()) {
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IntegerType intTy = intAttr.getType().cast<IntegerType>();
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APInt value = intAttr.getValue();
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// We omit the width specifier if the value is <= 32-bits in size, which
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// makes this more compatible with unknown width extmodules.
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if (intTy.getWidth() > 32) {
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// Sign comes out before any width specifier.
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if (intTy.isSigned() && value.isNegative()) {
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os << '-';
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value = -value;
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}
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if (intTy.isSigned())
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os << intTy.getWidth() << "'sd";
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else
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os << intTy.getWidth() << "'d";
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}
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value.print(os, intTy.isSigned());
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return {Symbol, intTy.isSigned() ? IsSigned : IsUnsigned};
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}
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if (auto strAttr = value.dyn_cast<StringAttr>()) {
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os << '"';
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os.write_escaped(strAttr.getValue());
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os << '"';
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return {Symbol, IsUnsigned};
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}
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if (auto fpAttr = value.dyn_cast<FloatAttr>()) {
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// TODO: relying on float printing to be precise is not a good idea.
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os << fpAttr.getValueAsDouble();
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return {Symbol, IsUnsigned};
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}
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if (auto verbatimParam = value.dyn_cast<ParamVerbatimAttr>()) {
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os << verbatimParam.getValue().getValue();
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return {Symbol, IsUnsigned};
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}
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if (auto parameterRef = value.dyn_cast<ParamDeclRefAttr>()) {
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os << parameterRef.getName().getValue();
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// TODO: Should we support signed parameters?
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return {Symbol, IsUnsigned};
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}
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// Handle nested expressions.
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auto expr = value.dyn_cast<ParamExprAttr>();
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if (!expr) {
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os << "<<UNKNOWN MLIRATTR: " << value << ">>";
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emitError() << " = " << value;
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return {LowestPrecedence, IsUnsigned};
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}
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StringRef operatorStr;
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VerilogPrecedence subprecedence = ForceEmitMultiUse;
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Optional<SubExprSignResult> operandSign;
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switch (expr.getOpcode()) {
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case PEO::Add:
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operatorStr = " + ";
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subprecedence = Addition;
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break;
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case PEO::Mul:
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operatorStr = " * ";
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subprecedence = Multiply;
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break;
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case PEO::And:
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operatorStr = " & ";
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subprecedence = And;
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break;
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case PEO::Or:
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operatorStr = " | ";
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subprecedence = Or;
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break;
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case PEO::Xor:
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operatorStr = " ^ ";
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subprecedence = Xor;
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break;
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case PEO::Shl:
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operatorStr = " << ";
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subprecedence = Shift;
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break;
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case PEO::ShrU:
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// >> in verilog is always a logical shift even if operands are signed.
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operatorStr = " >> ";
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subprecedence = Shift;
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break;
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case PEO::ShrS:
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// >>> in verilog is an arithmetic shift if both operands are signed.
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operatorStr = " >>> ";
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subprecedence = Shift;
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operandSign = IsSigned;
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break;
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case PEO::DivU:
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operatorStr = " / ";
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subprecedence = Multiply;
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operandSign = IsUnsigned;
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break;
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case PEO::DivS:
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operatorStr = " / ";
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subprecedence = Multiply;
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operandSign = IsSigned;
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break;
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case PEO::ModU:
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operatorStr = " % ";
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subprecedence = Multiply;
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operandSign = IsUnsigned;
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break;
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case PEO::ModS:
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operatorStr = " % ";
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subprecedence = Multiply;
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operandSign = IsSigned;
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break;
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}
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// Emit the specified operand with a $signed() or $unsigned() wrapper around
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// it if context requires a specific signedness to compute the right value.
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// This returns true if the operand is signed.
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// TODO: This could try harder to omit redundant casts like the mainline
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// expression emitter.
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auto emitOperand = [&](Attribute operand) -> bool {
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if (operandSign.hasValue())
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os << (operandSign.getValue() == IsSigned ? "$signed(" : "$unsigned(");
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auto signedness =
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printParamValue(operand, os, subprecedence, emitError).signedness;
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if (operandSign.hasValue()) {
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os << ")";
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signedness = operandSign.getValue();
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}
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return signedness == IsSigned;
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};
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if (subprecedence > parenthesizeIfLooserThan)
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os << '(';
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bool allOperandsSigned = emitOperand(expr.getOperands()[0]);
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for (auto op : ArrayRef(expr.getOperands()).drop_front()) {
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os << operatorStr;
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allOperandsSigned &= emitOperand(op);
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}
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if (subprecedence > parenthesizeIfLooserThan) {
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os << ')';
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subprecedence = Symbol;
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}
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return {subprecedence, allOperandsSigned ? IsSigned : IsUnsigned};
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}
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/// Prints a parameter attribute expression in a Verilog compatible way.
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/// This returns the precedence of the generated string.
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static SubExprInfo
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printParamValue(Attribute value, raw_ostream &os,
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function_ref<InFlightDiagnostic()> emitError) {
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return printParamValue(value, os, VerilogPrecedence::LowestPrecedence,
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emitError);
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}
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/// Return true for nullary operations that are better emitted multiple
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/// times as inline expression (when they have multiple uses) rather than having
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/// a temporary wire.
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@ -703,7 +546,7 @@ StringRef ModuleNameManager::addName(ValueOrOp valueOrOp, StringRef name) {
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}
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//===----------------------------------------------------------------------===//
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// VerilogEmitter
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// VerilogEmitterState
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//===----------------------------------------------------------------------===//
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namespace {
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@ -906,7 +749,16 @@ public:
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void emitBind(BindOp op);
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void emitBindInterface(BindInterfaceOp op);
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/// Prints a parameter attribute expression in a Verilog compatible way to the
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/// specified stream. This returns the precedence of the generated string.
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SubExprInfo printParamValue(Attribute value, raw_ostream &os,
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function_ref<InFlightDiagnostic()> emitError);
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public:
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SubExprInfo printParamValue(Attribute value, raw_ostream &os,
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VerilogPrecedence parenthesizeIfLooserThan,
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function_ref<InFlightDiagnostic()> emitError);
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/// This set keeps track of all of the expression nodes that need to be
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/// emitted as standalone wire declarations. This can happen because they are
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/// multiply-used or because the user requires a name to reference.
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@ -921,6 +773,163 @@ public:
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} // end anonymous namespace
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/// Prints a parameter attribute expression in a Verilog compatible way to the
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/// specified stream. This returns the precedence of the generated string.
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SubExprInfo
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ModuleEmitter::printParamValue(Attribute value, raw_ostream &os,
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function_ref<InFlightDiagnostic()> emitError) {
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return printParamValue(value, os, VerilogPrecedence::LowestPrecedence,
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emitError);
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}
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/// Helper that prints a parameter constant value in a Verilog compatible way.
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/// This returns the precedence of the generated string.
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SubExprInfo
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ModuleEmitter::printParamValue(Attribute value, raw_ostream &os,
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VerilogPrecedence parenthesizeIfLooserThan,
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function_ref<InFlightDiagnostic()> emitError) {
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if (auto intAttr = value.dyn_cast<IntegerAttr>()) {
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IntegerType intTy = intAttr.getType().cast<IntegerType>();
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APInt value = intAttr.getValue();
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// We omit the width specifier if the value is <= 32-bits in size, which
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// makes this more compatible with unknown width extmodules.
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if (intTy.getWidth() > 32) {
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// Sign comes out before any width specifier.
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if (intTy.isSigned() && value.isNegative()) {
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os << '-';
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value = -value;
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}
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if (intTy.isSigned())
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os << intTy.getWidth() << "'sd";
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else
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os << intTy.getWidth() << "'d";
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}
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value.print(os, intTy.isSigned());
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return {Symbol, intTy.isSigned() ? IsSigned : IsUnsigned};
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}
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if (auto strAttr = value.dyn_cast<StringAttr>()) {
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os << '"';
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os.write_escaped(strAttr.getValue());
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os << '"';
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return {Symbol, IsUnsigned};
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}
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if (auto fpAttr = value.dyn_cast<FloatAttr>()) {
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// TODO: relying on float printing to be precise is not a good idea.
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os << fpAttr.getValueAsDouble();
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return {Symbol, IsUnsigned};
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}
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if (auto verbatimParam = value.dyn_cast<ParamVerbatimAttr>()) {
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os << verbatimParam.getValue().getValue();
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return {Symbol, IsUnsigned};
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}
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if (auto parameterRef = value.dyn_cast<ParamDeclRefAttr>()) {
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os << parameterRef.getName().getValue();
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// TODO: Should we support signed parameters?
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return {Symbol, IsUnsigned};
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}
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// Handle nested expressions.
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auto expr = value.dyn_cast<ParamExprAttr>();
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if (!expr) {
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os << "<<UNKNOWN MLIRATTR: " << value << ">>";
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emitError() << " = " << value;
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return {LowestPrecedence, IsUnsigned};
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}
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StringRef operatorStr;
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VerilogPrecedence subprecedence = ForceEmitMultiUse;
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Optional<SubExprSignResult> operandSign;
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switch (expr.getOpcode()) {
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case PEO::Add:
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operatorStr = " + ";
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subprecedence = Addition;
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break;
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case PEO::Mul:
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operatorStr = " * ";
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subprecedence = Multiply;
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break;
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case PEO::And:
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operatorStr = " & ";
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subprecedence = And;
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break;
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case PEO::Or:
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operatorStr = " | ";
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subprecedence = Or;
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break;
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case PEO::Xor:
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operatorStr = " ^ ";
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subprecedence = Xor;
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break;
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case PEO::Shl:
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operatorStr = " << ";
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subprecedence = Shift;
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break;
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case PEO::ShrU:
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// >> in verilog is always a logical shift even if operands are signed.
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operatorStr = " >> ";
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subprecedence = Shift;
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break;
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case PEO::ShrS:
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// >>> in verilog is an arithmetic shift if both operands are signed.
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operatorStr = " >>> ";
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subprecedence = Shift;
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operandSign = IsSigned;
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break;
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case PEO::DivU:
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operatorStr = " / ";
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subprecedence = Multiply;
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operandSign = IsUnsigned;
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break;
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case PEO::DivS:
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operatorStr = " / ";
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subprecedence = Multiply;
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operandSign = IsSigned;
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break;
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case PEO::ModU:
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operatorStr = " % ";
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subprecedence = Multiply;
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operandSign = IsUnsigned;
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break;
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case PEO::ModS:
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operatorStr = " % ";
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subprecedence = Multiply;
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operandSign = IsSigned;
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break;
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}
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// Emit the specified operand with a $signed() or $unsigned() wrapper around
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// it if context requires a specific signedness to compute the right value.
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// This returns true if the operand is signed.
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// TODO: This could try harder to omit redundant casts like the mainline
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// expression emitter.
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auto emitOperand = [&](Attribute operand) -> bool {
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if (operandSign.hasValue())
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os << (operandSign.getValue() == IsSigned ? "$signed(" : "$unsigned(");
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auto signedness =
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printParamValue(operand, os, subprecedence, emitError).signedness;
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if (operandSign.hasValue()) {
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os << ')';
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signedness = operandSign.getValue();
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}
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return signedness == IsSigned;
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};
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if (subprecedence > parenthesizeIfLooserThan)
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os << '(';
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bool allOperandsSigned = emitOperand(expr.getOperands()[0]);
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for (auto op : ArrayRef(expr.getOperands()).drop_front()) {
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os << operatorStr;
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allOperandsSigned &= emitOperand(op);
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}
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if (subprecedence > parenthesizeIfLooserThan) {
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os << ')';
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subprecedence = Symbol;
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}
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return {subprecedence, allOperandsSigned ? IsSigned : IsUnsigned};
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}
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//===----------------------------------------------------------------------===//
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// Expression Emission
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//===----------------------------------------------------------------------===//
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@ -1514,7 +1523,7 @@ SubExprInfo ExprEmitter::visitTypeOp(ConstantOp op) {
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}
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SubExprInfo ExprEmitter::visitTypeOp(ParamValueOp op) {
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return printParamValue(op.value(), os, [&]() {
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return emitter.printParamValue(op.value(), os, [&]() {
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return op->emitOpError("invalid parameter use");
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});
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}
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@ -2680,7 +2689,7 @@ LogicalResult StmtEmitter::visitStmt(InstanceOp op) {
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}
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os.indent(state.currentIndent + INDENT_AMOUNT)
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<< prefix << '.' << param.getName().getValue() << '(';
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printParamValue(param.getValue(), os, [&]() {
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emitter.printParamValue(param.getValue(), os, [&]() {
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return op->emitOpError("invalid instance parameter '")
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<< param.getName().getValue() << "' value";
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});
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@ -3019,7 +3028,7 @@ void StmtEmitter::collectNamesEmitDecls(Block &block) {
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if (auto localparam = dyn_cast<LocalParamOp>(op)) {
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os << " = ";
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printParamValue(localparam.value(), os, [&]() {
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emitter.printParamValue(localparam.value(), os, [&]() {
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return op->emitOpError("invalid localparam value");
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});
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}
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