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Fix enabling of AArch64 user-level cache ops 

These operations should be possible on seL4 with and without hypervisor
mode.

Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
This commit is contained in:
Ivan-Velickovic 2023-06-14 12:06:08 +10:00 committed by Kent McLeod
parent 1ca227a1b5
commit 0792eebc0a
1 changed files with 1 additions and 1 deletions
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src/arch/arm/64/head.S
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@ -23,7 +23,7 @@
#define CR_ALIGN_CLEAR 0
#endif
#if defined(CONFIG_ARM_HYPERVISOR_SUPPORT) && defined(CONFIG_AARCH64_USER_CACHE_ENABLE)
#if !defined(CONFIG_ARM_HYPERVISOR_SUPPORT) && defined(CONFIG_AARCH64_USER_CACHE_ENABLE)
#define CR_USER_CACHE_OPS_SET (BIT(CONTROL_UCT) | BIT(CONTROL_UCI))
#define CR_USER_CACHE_OPS_CLEAR 0
#else