Update code from upstream repository
https://github.com/chipsalliance/riscv-dv to revision
71666ebacd69266b1abb7cdbad5e1897ce5884e6
* Fixes to support RV32 (Maciej Kurc)
* Extend CI matrix (Eryk Szpotanski)
* Add pyflow test (Grzegorz Placzek)
* Allow the CI to run from any branch and any PR (Maciej Kurc)
* [pmp] Remove MSECCFG reads from trap handler when Smepmp is disabled
(Marno van der Maas)
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
The gen_csr_test.py script provided by RISC-V DV doesn't work with
version 4.0 and upwards of the bitstring library. This patch pins it to
3.1.9 to avoid the issue.
With the latest versions of all python packages in
python-requirements.txt ibex_cmd.py was seeing a run-time type error.
Data from a YAML file that had previously always been a string could now
be an int as well. This alters the code to allow the int to work.
It turns out that we use split_var in the code, which was added in
version 4.030 (and several bugs were fixed in following versions).
Change the minimum required version to match what we're using in
CI (and presumably works!)
This was triggered by issue #2080.
This shouldn't change the behaviour when it works. On a failure, we
now print out a bit more about what's going on.
When asked to do something impossible now, I think the output is a bit
clearer. For example, if you try to run riscv_bitmanip_full_test with
an OpenTitan configuration (which doesn't have full bitmanip), the
warning message is now:
WARNING:ibex_cmd:Rejecting test: riscv_bitmanip_full_test. It specifies rtl_params of ['ibex_pkg::RV32BFull'], which doesn't contain the expected 'ibex_pkg::RV32BOTEarlGrey'.
(The following stuff that appears is a bit messy, but at least the
first line is now clearer!)
The recent versions of Verible that I've tried die when they are given
an empty waiver file. The error message is "Fatal error: Broken waiver
config handle". I can't see a way to add a comment ("// No waiver" or
similar), so I think the best way to keep everything alive is to
delete the empty file.
The background of the Icache block was a not-well-fitted path that was
causing the background to seep through. This commit updates that
background to more tightly align with the lines and letters.
The background was originally a gradient background on the right
together with a solid background on the left. This caused some
distortion on closer inspection. This commit changes it to have one
background that is a gradient from left to right.
Running the verible linter and adding review comments to the pull
request previously had to be done in two stages:
1. Triggered on the pull request - prepare config and waiver files as
artifacts.
2. Running on the repo's HEAD - run Verible and add review comments.
This was required because Actions running in the context of the pull
request did not have write permissions to add comments to pull requests.
This is now possible with the `pull_request_target` event, which
triggers when pull requests change, but runs in the context of the
repo's HEAD and has the permissions to create comments.
See lowRISC/ibex#1427 and
chipsalliance/verible-linter-action#31 for details.
Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
Update code from upstream repository
https://github.com/chipsalliance/riscv-dv to revision
08b12066b34c9728f706e45098ba502a36d7ca59
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
Update code from upstream repository https://github.com/lowrisc/riscv-
isa-sim to revision a4b823a1c7a260b532e1aa41b4d929e9634a7222
* Remove personal paths from Makefile (Marno van der Maas)
* Remove trailing whitespace (Marno van der Maas)
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
Update code from upstream repository https://github.com/lowrisc/riscv-
isa-sim to revision a7c5d5d830e4095aa86580579efc46335fbc2f80
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
This initialisation causes Xcelium to complain about multiple drivers
for the variable. Which is rather confusing, but we don't actually
need to initialise it: the variable will be X at the start of time, so
the logic that stops the simulation if it gets big won't fire until
after reset anyway.
The ibex_top_tracing module takes a ram_cfg_i for something to pass
through to the RAM. Use the named zero (RAM_1P_CFG_DEFAULT) instead of
building it by hand: now we get the right width.
This helps hit more coverage more reliably in particular for the
priv_mode_irq_cross cross coverage.
A better fix would adjust riscv_mem_intg_error_test to utilize U mode
more but it's a quick test for run so this suffices for now.
Not doing so causes VCS to spit out a warning message. The intention
seems to be that the initial call to $value$plusargs will evaluate to
true and will put the value that was assigned into the
disable_pmp_exception_handler variable, which then gets checked.
The previous version doesn't make sense if you read the classes in
exactly the order they are defined in the file. It turns out that this
is what VCS did: oops! Fortunately, the fix is pretty trivial: declare
the classes the other way around.
The previous code caused VCS to complain that the "with" clause didn't
use any of the constituent coverpoints. I *think* that VCS wasn't
understanding that cp_interrupt_taken[5:4] does indeed depend on
cp_interrupt_taken (concentrating on core_ibex_fcov_if for
concreteness).
Fortunately, the check is easy to express a different way. There, we
were just asking that the top two bits are zero. Another way to say
that is "if I shift everything else off the bottom, the result is
zero". So we say it that way.
This causes VCS to spit out an error because it's not technically
allowed in SystemVerilog. The only things that we needed to import
seems to have been the CSR_MHPMCOUNTER3* names. We can just refer to
them explicitly.
Other code tries to pick up things like DATA_WIDTH through this agent
package, that it imports. That doesn't seem unreasonable, but VCS
complains because we're not re-exporting it here.
Some code we've got in Ibex uses some stuff we added to Spike last
October. That, in turn, is now tagged in our riscv-isa-sim repository
as ibex-cosim-v0.5. Update the version requirement here to match.
It seems that typeguard now spots if env happens to be None. We can
just relax things: we're only using env by passing it through to
subprocess.run, which handles a None env in the expected way.
We ended up with the Unicode fix twice because of two colliding PR
merges. We only need one copy of the -CFLAGS argument, and VCS
generates a rather strange message about an unknown argument if you
use it twice. Fortunately, it's easy to fix once you've worked out how
to get the system to print out what it's doing.
Cairo libraries are required for a python dependency.
New RTD config introduced to fix build errors introduced by new urllib.
We need to ensure the docs a built on a modern ubuntu with a
sufficiently new python (see
https://github.com/readthedocs/readthedocs.org/issues/10290).
Previously any changes in interrupt state or debug requests were
strictly associated with retired instructions. This causes cosim
mismatches where a lower priority interrupt occurs in time before a
higher priority interrupt or debug request but between instruction
fetches/retirements so both the low and high priority interrupts are
signalled with the instruction retirement.
This introduces a way for the RVFI to signal an interrupt has occurred
that isn't associated with an instruction retirement to allow the cosim
to see the seperation in time between different interrupts and debug
requests and hence model behaviour correctly.
An IRQ asserting then deasserting when not explictly cleared by an
interrupt handler can lead to RTL/cosim mismatches in some cases.
Increasing the delay here minimises those instances.
- rvfi_trap now correctly handled for writeback
- issue created to track coverpoint for pmpcfg reserved bits writes.
- flush pipe on debug CSR writes is reasonable
Michael Schaffner