mirror of https://github.com/Qiskit/qiskit.git
310 lines
11 KiB
Python
310 lines
11 KiB
Python
# This code is part of Qiskit.
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#
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# (C) Copyright IBM 2021.
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#
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# This code is licensed under the Apache License, Version 2.0. You may
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# obtain a copy of this license in the LICENSE.txt file in the root directory
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# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
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#
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# Any modifications or derivative works of this code must retain this
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# copyright notice, and modified files need to carry a notice indicating
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# that they have been altered from the originals.
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"""Test RemoveFinalMeasurements pass"""
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import unittest
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from qiskit import ClassicalRegister, QuantumRegister, QuantumCircuit
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from qiskit.circuit import Clbit
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from qiskit.transpiler.passes import RemoveFinalMeasurements
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from qiskit.converters import circuit_to_dag
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from qiskit.transpiler.passes.utils.remove_final_measurements import calc_final_ops
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from test import QiskitTestCase # pylint: disable=wrong-import-order
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class TestRemoveFinalMeasurements(QiskitTestCase):
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"""Test removing final measurements."""
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def test_multi_bit_register_removed_with_clbits(self):
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"""Remove register when all clbits removed."""
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def expected_dag():
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q0 = QuantumRegister(2, "q0")
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qc = QuantumCircuit(q0)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(2, "q0")
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c0 = ClassicalRegister(2, "c0")
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qc = QuantumCircuit(q0, c0)
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# measure into all clbits of c0
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qc.measure(0, 0)
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qc.measure(1, 1)
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertFalse(dag.cregs)
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self.assertFalse(dag.clbits)
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self.assertEqual(dag, expected_dag())
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def test_overlapping_register_removal(self):
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"""Only registers that become idle directly as a result of
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final op removal are removed. In this test, a 5-bit creg
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is implicitly created with its own bits, along with cregs
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``c0_lower_3`` and ``c0_upper_3`` which reuse those underlying bits.
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``c0_lower_3`` and ``c0_upper_3`` reference only 1 bit in common.
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A final measure is performed into a bit that exists in ``c0_lower_3``
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but not in ``c0_upper_3``, and subsequently is removed. Consequently,
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both ``c0_lower_3`` and the 5-bit register are removed, because they
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have become unused as a result of the final measure removal.
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``c0_upper_3`` remains, because it was idle beforehand, not as a
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result of the measure removal, along with all of its bits,
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including the bit shared with ``c0_lower_3``."""
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def expected_dag():
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q0 = QuantumRegister(3, "q0")
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c0 = ClassicalRegister(5, "c0")
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c0_upper_3 = ClassicalRegister(name="c0_upper_3", bits=c0[2:])
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# note c0 is *not* added to circuit!
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qc = QuantumCircuit(q0, c0_upper_3)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(3, "q0")
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c0 = ClassicalRegister(5, "c0")
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qc = QuantumCircuit(q0, c0)
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c0_lower_3 = ClassicalRegister(name="c0_lower_3", bits=c0[:3])
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c0_upper_3 = ClassicalRegister(name="c0_upper_3", bits=c0[2:])
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# Only qc.clbits[2] is shared between the two.
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qc.add_register(c0_lower_3)
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qc.add_register(c0_upper_3)
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qc.measure(0, c0_lower_3[0])
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertListEqual(list(dag.cregs.values()), [c0_upper_3])
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self.assertListEqual(dag.clbits, list(c0_upper_3))
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self.assertEqual(dag, expected_dag())
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def test_multi_bit_register_removed_if_all_bits_idle(self):
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"""A multibit register is removed when all bits are idle."""
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def expected_dag():
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q0 = QuantumRegister(1, "q0")
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qc = QuantumCircuit(q0)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(1, "q0")
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c0 = ClassicalRegister(2, "c0")
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qc = QuantumCircuit(q0, c0)
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# measure into single bit c0[0] of c0
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qc.measure(0, 0)
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertFalse(dag.cregs)
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self.assertFalse(dag.clbits)
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self.assertEqual(dag, expected_dag())
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def test_multi_reg_shared_bits_removed(self):
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"""All registers sharing removed bits should be removed."""
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def expected_dag():
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q0 = QuantumRegister(2, "q0")
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qc = QuantumCircuit(q0)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(2, "q0")
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c0 = ClassicalRegister(2, "c0")
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qc = QuantumCircuit(q0, c0)
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# Create reg with shared bits (same as c0)
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c1 = ClassicalRegister(name="c1", bits=qc.clbits)
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qc.add_register(c1)
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# measure into all clbits of c0
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qc.measure(0, c0[0])
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qc.measure(1, c0[1])
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertFalse(dag.cregs)
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self.assertFalse(dag.clbits)
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self.assertEqual(dag, expected_dag())
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def test_final_measures_share_dest(self):
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"""Multiple final measurements use the same clbit."""
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def expected_dag():
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qc = QuantumCircuit(QuantumRegister(2, "q0"))
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return circuit_to_dag(qc)
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rq = QuantumRegister(2, "q0")
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rc = ClassicalRegister(1, "c0")
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qc = QuantumCircuit(rq, rc)
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qc.measure(0, 0)
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qc.measure(1, 0)
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertEqual(dag, expected_dag())
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def test_remove_chained_final_measurements(self):
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"""Remove successive final measurements."""
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def expected_dag():
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q0 = QuantumRegister(1, "q0")
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q1 = QuantumRegister(1, "q1")
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c0 = ClassicalRegister(1, "c0")
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qc = QuantumCircuit(q0, c0, q1)
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qc.measure(q0, c0)
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qc.measure(q0, c0)
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qc.barrier()
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qc.h(q1)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(1, "q0")
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q1 = QuantumRegister(1, "q1")
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c0 = ClassicalRegister(1, "c0")
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c1 = ClassicalRegister(1, "c1")
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qc = QuantumCircuit(q0, c0, q1, c1)
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qc.measure(q0, c0)
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qc.measure(q0, c0)
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qc.barrier()
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qc.h(q1)
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qc.measure(q1, c1)
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qc.measure(q0, c1)
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertEqual(dag, expected_dag())
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def test_remove_clbits_without_register(self):
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"""clbits of final measurements not in a register are removed."""
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def expected_dag():
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q0 = QuantumRegister(1, "q0")
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qc = QuantumCircuit(q0)
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return circuit_to_dag(qc)
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q0 = QuantumRegister(1, "q0")
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qc = QuantumCircuit(q0)
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# Add clbit without adding register
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qc.add_bits([Clbit()])
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self.assertFalse(qc.cregs)
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# Measure to regless clbit
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qc.measure(0, 0)
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertFalse(dag.cregs)
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self.assertFalse(dag.clbits)
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self.assertEqual(dag, expected_dag())
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def test_final_barriers_and_measures_complex(self):
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"""Test complex final barrier and measure removal."""
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def expected_dag():
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q0 = QuantumRegister(5, "q0")
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c1 = ClassicalRegister(1, "c1")
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qc = QuantumCircuit(q0, c1)
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qc.h(q0[0])
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return circuit_to_dag(qc)
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# ┌───┐┌─┐ ░ ░ ┌─┐
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# q0_0: ┤ H ├┤M├─░─────░─┤M├───────────────
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# └┬─┬┘└╥┘ ░ ░ └╥┘┌─┐
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# q0_1: ─┤M├──╫──░─────░──╫─┤M├────────────
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# └╥┘ ║ ░ ░ ░ ║ └╥┘┌─┐
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# q0_2: ──╫───╫──░──░──░──╫──╫─┤M├─────────
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# ║ ║ ░ ░ ░ ║ ║ └╥┘┌─┐
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# q0_3: ──╫───╫──░──░──░──╫──╫──╫─┤M├──────
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# ║ ║ ░ ░ ░ ║ ║ ║ └╥┘┌─┐ ░
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# q0_4: ──╫───╫──░─────░──╫──╫──╫──╫─┤M├─░─
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# ║ ║ ░ ░ ║ ║ ║ ║ └╥┘ ░
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# c0: 1/══╩═══╩═══════════╬══╬══╬══╬══╬════
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# 0 0 ║ ║ ║ ║ ║
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# ║ ║ ║ ║ ║
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# c1: 1/══════════════════╬══╬══╬══╬══╬════
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# ║ ║ ║ ║ ║
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# meas: 5/════════════════╩══╩══╩══╩══╩════
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# 0 1 2 3 4
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q0 = QuantumRegister(5, "q0")
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c0 = ClassicalRegister(1, "c0")
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c1 = ClassicalRegister(1, "c1")
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qc = QuantumCircuit(q0, c0, c1)
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qc.measure(q0[1], c0)
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qc.h(q0[0])
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qc.measure(q0[0], c0[0])
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qc.barrier()
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qc.barrier(q0[2], q0[3])
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qc.measure_all()
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qc.barrier(q0[4])
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dag = circuit_to_dag(qc)
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dag = RemoveFinalMeasurements().run(dag)
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self.assertEqual(dag, expected_dag())
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def test_calc_final_ops(self):
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"""Test method to find the final operations in a circuit."""
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q0 = QuantumRegister(5, "q0")
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c0 = ClassicalRegister(1, "c0")
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c1 = ClassicalRegister(1, "c1")
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qc = QuantumCircuit(q0, c0, c1)
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# ┌───┐┌─┐ ░
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# q0_0: ┤ H ├┤M├─░────
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# └┬─┬┘└╥┘ ░
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# q0_1: ─┤M├──╫──░────
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# └╥┘ ║ ░
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# q0_2: ──╫───╫──░────
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# ║ ║ ░ ┌─┐
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# q0_3: ──╫───╫──░─┤M├
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# ║ ║ ░ └╥┘
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# q0_4: ──╫───╫──░──╫─
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# ║ ║ ░ ║
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# c0: 1/══╩═══╩═════╬═
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# 0 0 ║
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# c1: 1/════════════╩═
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# 0
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qc.measure(q0[1], c0)
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qc.h(q0[0])
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qc.measure(q0[0], c0)
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qc.barrier()
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qc.measure(q0[3], c1)
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final_measurements = [
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node.qargs for node in calc_final_ops(circuit_to_dag(qc), {"measure"})
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]
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self.assertEqual([(q0[3],)], final_measurements)
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final_measurements_barriers = calc_final_ops(circuit_to_dag(qc), {"measure", "barrier"})
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self.assertEqual(len(final_measurements_barriers), 4)
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final_barriers = calc_final_ops(circuit_to_dag(qc), {"barrier"})
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self.assertEqual(final_barriers, [])
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if __name__ == "__main__":
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unittest.main()
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