* set T2 with the correct value in ConfigurableFakeBackend
* minor clean up and add to release notes
* Reword release note
Co-authored-by: Jake Lishman <jake.lishman@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Add function to easily generate preset pass managers
This commit adds a new function, generate_preset_pass_managers(), which
is used to quickly generate the preset pass manager for manual
interaction. Prior to this new function there were lower level functions
which are used to generate the individual pass manager objects for each
optimization level but they are hidden behind an abstraction object,
PassManagerConfig which is the only input. This makes it harder to work
with because the user has to manually remember to generate the config
object prior to creating the pass manager. Similarly this new function
simplifies the creation of preset pass managers by having a single entry
point instead of 4 for each optimization level.
* Add target override support if manually specified
If a user manually specifies a Target object to use as the compilation
target we still need to generate the old data structures to trigger
some passes to run. We also want the properties of the target to
supersede those in a specified backend if it's manually specified. This
commit corrects the handling of this so the manually specified target is
the source of truth when specified.
* Deduplicate shared argument list
* Expand test coverage
* Fix cyclic import issues
* Apply suggestions from code review
Co-authored-by: Julien Gacon <gaconju@gmail.com>
Co-authored-by: Julien Gacon <gaconju@gmail.com>
* Make python-constraint optional
Since #7213 we no longer have been using the CSPLayout pass by default
in the preset passmanagers or transpile(). This is because it has been
superseded by the VF2Layout pass which is now used everywhere. While we
will keep the CSPLayout pass around for the forseeable future there is
no need to install python-constraint by default anymore since it's only
user is the CSPLayout pass, which isn't going to be commonly used
anymore now that it's not used in the default compilation path anymore.
This commit removes the python-constraint library from the requirements
list and makes it an optional dependency.
Fixes#7726
* Add docstring for HAS_CONSTRAINT
* Add private module to avoid module level optional import
This commit splits the custom solver class definition out into a
separate private module that is not imported until runtime. This enables
us to avoid a module level import for python-constraint meaning we only
try to import if something is actually using CSPLayout.
* Fix rebase issue
* Fix lint
* Fix typo in release note
Co-authored-by: Steve Wood <40241007+woodsp-ibm@users.noreply.github.com>
* Alphabetize optionals list
Co-authored-by: Steve Wood <40241007+woodsp-ibm@users.noreply.github.com>
* Add string representation for PassManagerConfig
This commit adds a new string representation to the PassManagerConfig
class. When str() is run on a PassManagerConfig object it will return a
string listing the values for all of the attributes in the class.
* Adjust tab indent and add tests
This commit ensure that all entries under the pass manager config have a
single tab indent and also adds a test to verify the output.
* Improve performance of `SparsePauliOp.__init__`
* add `_count_y` utility function (w/ default dtype=np.uint8)
* optimize the phase computation part of `SparsePauliOp.__init__`
* fix add of uint8 and int64
* use np.min_scale_type
* fix axis
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Improve reverse_bits to support registerless bits
* Change the algorithm of reverse_bits
* Reimplement reverse_bits with reversed bits
Also add more test cases.
* Simplify bit lookups
Co-authored-by: Jake Lishman <jake.lishman@ibm.com>
Commit 84cfd5c1 recently used a `&[char; 2]` as the type in the
constructor of the `std::Pattern` trait, which is a feature of Rust
unstable, and only available in newer versions of Rust. We've not fixed
an absolute minimum supported Rust version, but have generally tried to
keep things building with at least the last six months' releases.
* Add a marginal_distribution function
This commit adds a new function marginal_distribution which performs
marginalization similar to the existing marginal_counts() function. This
new function however differs in a few key ways. Most importantly the order
of the bit indices is significant for the purpose of permuting the bits
while marginalizing, while marginal_counts() doesn't do this.
Additionally, this function only works with dictionaries and not Result
objects and is written in Rust for performance. While the purposed of
this function is mostly identical to marginal_counts(), because making
the bit indices order significant is a breaking change this was done as
a separate function to avoid that. Once this new function is released
we can look at deprecated and eventually removing the existing
marginal_counts() function.
Fixes#6230
* Fix typos in python function
* Handle missing indices
In case a bit string has stripped leading zeros this commit adds
handling to treat a missing index from the bit string as a '0'.
* Apply suggestions from code review
Co-authored-by: Jake Lishman <jake@binhbar.com>
* Remove unecessary rust index
* Update test
Co-authored-by: Jake Lishman <jake@binhbar.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
While this function accepts a URL, it is not essential for basic
use, and it is not clear from the IBM Q account what URL should
be used.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Avoid UnitarySynthesis plugin discovery overhead with no method set
This commit tweaks the logic around loading plugins in the
UnitarySynthesis transpiler pass. Previously we would unconditionally
perform plugin discovery in all cases even if no custom plugin was
specified. This added some overhead the first time we initialize a
UnitarySynthesis pass object to do the initial discovery, import, and
initialization of any installed plugins. While typically this is fast
(locally just with the 2 plugins including in terra this takes ~.04
seconds) it does depend on the performance of all the installed plugins.
However, this overhead is not necessary if there is not a custom
synthesis method requested by a user. If the default method is being
used we can just directly instatiate the plugin and avoid the discovery
process. This commit changes the UnitarySynthesis pass to only run
discovery if the method argument is set to something other than
"default".
* Fix lint failure
* Fix SabreSwap with classically conditioned gates
The calculation of the expected number of predecessors for a gate to
be considered "resolved" in `SabreSwap` was not accounting for wires
stemming from classical conditions. The tracking of the _actual_ number
of predecessor requirements satisfied did correctly account for this, so
in certain circumstances the actual count could jump from "too low" to
"too high" without passing through "just right", and the gate would
never get added to the circuit.
* Use `successors` to calculate required predecessors
This unifies the calculation of what is considered a required
predecessor by using the same `SabreSwap._successors` function for both
aspects of the comparison: counting the required predecessors and
counting the actual number of applied predecessors. This simplifies the
logic, since now an update in one place is sufficient, and the wires are
read directly from the DAG, rather than using assumptions about the
nodes.
* Fix incorrect import
* Fix decremented typo
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
The marginalisation could previously return the empty string instead of
`"0"` if the given indices were too high for a given memory slot,
causing a later error in binary-to-hex conversion.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Document modifications to the release process
This commit updates the CONTRIBUTING.md file to more clearly document
the current release process. Previously for the release cycle
documentation we just had a mechanical list of the steps done by the
core team and what the automation does but it didn't really contain any
details on the aspects of how contributions with releasing. This commit
updates this section to better describe the different phases of a
release and the expectations and order of operations a contributor will
need to know around releasing.
* Update CONTRIBUTING.md
Co-authored-by: Lev Bishop <18673315+levbishop@users.noreply.github.com>
* Update CONTRIBUTING.md
Co-authored-by: Lev Bishop <18673315+levbishop@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* * Renamed directory.
* * Typo.
* * Commuting2qBlocks name
* * logical -> virtual.
* * from_line in the example.
* * Reno name fix.
* * Reno rewording.
* * removed unnecessary line in example.
* * Black.
* * Started designing test on non-line graph.
* * Added test on a T device.
* * Renamed Communting2qBlocks to Commuting2qBlock
* * Made test robust to arbitraryness of commuting gate order.
* Added test.
* * Added test and black.
* * Fix missing gate test exception refactor.
* * Bug fix with test.
* * Removed SwapStrategy from the passes init.
* * black
* convert dtm from nanoseconds to seconds
* Handle dtm not defined in configuration
* Add test for checking backend v2 dtm less than 1e-6
* add release note
* new line in release note
* Update qiskit/test/mock/fake_backend.py
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Deduplicate and unify VF2 layout passes
In #7862 we recently added a new vf2 post layout pass which is designed
to run after routing to improve the layout once we know there is at
least one isomorphic subgraph in the coupling graph for the interactions
in the circuit. In that PR we still ran vf2 post layout even if vf2
layout pass found a match. That's because the heuristic scoring of
layouts used for the vf2 layout and vf2 post layout passes were
different. Originally this difference was due to the the vf2 post
layout pass being intedended to run after the optimization loop where we
could guarantee the gates were in the target and exactly score the error
for each potential layout. But since the vf2 post layout was updated to
score a layout based on the gate counts for each qubit and the average
1q and 2q instruction error rates we can leverage this better heuristic
scoring in the vf2 layout pass. This commit updates the vf2 layout pass
to use the same heuristic and deduplicates some of the code between the
passes at the same time. Additionally, since the scoring heuristics are
the same the preset pass managers are updated to only run vf2 post
layout if vf2 layout didn't find a match. If vf2 layout finds a match
it's going to be the same as what vf2 post layout finds so there is no
need to run the vf2 post layout pass anymore.
* Update apply post layout condition comments
* Remove old layout score function
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Remove hard time limit from vf2 passes in preset passmanagers
This commit removes the hard time limit from the preset passmanager. We
were previously setting two limits on the pass a call_limit parameter,
which is used to set the limit of internal state visits the vf2
implementation in retworkx will attempt before giving up, and a time
limit which sets a hard wall time limit that is checked after each
mapping to ensure we don't spend more than a specific amount of time on
trying to find an optimal mapping. As subgraph isomorphism is
NP-complete we could spend a very large amount of time trying to find
the next isomorphic mapping and both these limits were set to avoid a
situation where we spend hours in optimization level 1 trying to find a
better layout. However, as we've seen in #8017 setting a hard time limit
limits the level of reproducibility on the output of the transpiler. It
means that setting a fixed seed is no longer sufficient to exactly
reproduce the output as it's also partially a function of the
performance of the local system we're running on. If the local
environment is slower we might get different results because we've hit
the hard time limit.
To address this, this commit removes the hard time limit so that we only
rely on the call limit parameter on the preset pass manager. While this
parameter is a bit more opaque in how it should be used because it
requires an understanding of how the VF2 algorithm works (and is
implemented in retworkx) it should be sufficient to avoid the runaway
execution problem but also means the limits are determinitisically
applied. This should improve the reproducability of the transpiler because
the pass will always try exactly up until a given point regardless of
how fast the local environment is.
For people manually instatiating the pass they can still rely on the
hard time limit parameter if they want it, but for the preset pass
managers and the transpile() function we no longer set this.
Fixes#8017
* Add release note
* Fix tense
Co-authored-by: Jake Lishman <jake@binhbar.com>
* Support target and basis gates in Unroll3qOrMore transpiler pass
This commit adds two new constructor arguments to the Unroll3qOrMore
transpiler pass, target and basis_gates, which are used to specify a
backend target and basis gate list respectively. If these are specified
the pass will not decompose any multiqubit operations present in the
circuit if they are in the target or basis_gates list.
Fixes#5518
Related to #7812
Part of #7113
* Update releasenotes/notes/unroll3q-target-bf57cc4365808862.yaml
Co-authored-by: Naoki Kanazawa <nkanazawa1989@gmail.com>
* Fix lint
* Fix release-note typo
Co-authored-by: Naoki Kanazawa <nkanazawa1989@gmail.com>
Co-authored-by: Jake Lishman <jake@binhbar.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Add missing delay instruction to fake backends
This commit adds the delay instruction to the target for fake backends
based on BackendV2. With BackendV2 and the Target delay isn't assumed to
be present on every backend and it has to be explictly listed. This
commit fixes this so that the compiler is aware that delay is a valid
operation (without any additional constraints) on the BackendV2 based
fake backends.
* Add qubits to Delay target entry
If any instructions available in a target are ideal, with no qubits or
properties set, the target class assumes the backend is ideal (like in
the case of an ideal simulator where are all instructions are globally
defined and have no error or duration). To avoid this we need to define
the Delay instruction on all qubits explicitly. This commit makes this
change to ensure the target for backends still shows the qubits and
properties for the other operations. However, in adding an instruction
with no properties defined a bug in the plot gate error map function was
uncovered where it errored because it assumes all instructions have
properties defined, this was fixed at the same time.
* Add release note
* Update releasenotes/notes/delay-fake-backends-3f68c074e85d531f.yaml
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Fixing issue #7634
At this point, there is an arbitrary number for the maximum shots in the BasicAer simulator "65536". The solution proposed @kevinsung is to work with zero as the default value of max_shots. This solves the problem with the evaluation of max_shots in the assemble function "_parse_common_args" in qiskit/compiler/assembler.py.
* Update backend.py
* Update backend.py
* Update backend.py
* adding test
correcting some errors about where to add the test.
* Create remove-basicaer-shot-limit-b7cd4e6f6739885c.yaml
* Update releasenotes/notes/remove-basicaer-shot-limit-b7cd4e6f6739885c.yaml
Co-authored-by: Kevin J. Sung <kevinjefferysung@gmail.com>
* Remove test of shot limit
The test previously just ran `BasicAer` with two million shots on the
transpiled circuit to see if it encountered a limit. This is simple
enough functionality (and unlikely enough to be broken accidentally)
that it can do without a test - the previous one took about 8 seconds,
which is a long time for testing a toggle.
Co-authored-by: Kevin J. Sung <kevinjefferysung@gmail.com>
Co-authored-by: Jake Lishman <jake.lishman@ibm.com>
* Remove DAGNode deprecations
* Remove name from DAGNode
* Remove unused import
* Add release note and put name getter and setter back
* Fix name setter and getter
* Remove DAGNode name getter and setter
* Update releasenotes/notes/remove-dagnode-deprecations-30703a2156d52b8a.yaml
Co-authored-by: Kevin Krsulich <kevin@krsulich.net>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* `passenv` `RAYON_NUM_THREADS` in `tox.ini`
This allows setting the number of rayon threads used by tox by
passing through `RAYON_NUM_THREADS`, so that the user is not
required to also specify `TOX_TESTENV_PASSENV=RAYON_NUM_THREADS`.
* Update tox.ini
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
* Remove duplicate `OMP_`
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Fix instruction durations in transpile() with BackendV2
When running transpile() with BackendV2 based backends the instruction
durations property from the backend would not be processed correctly
resulting in the absence of the default durations for instructions
supported on the target backend. This commit fixes this by correctly
handling BackendV2 based backends and using those instruction durations
by default for transpile().
* Update test/python/compiler/test_transpiler.py
Co-authored-by: Kevin Hartman <kevin@hart.mn>
Co-authored-by: Kevin Hartman <kevin@hart.mn>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* Multilpy dt value by conversion factor when reading from conf file.
* Add simple test and release note.
* Update releasenotes/notes/fix-target-dt-4d306f1e9b07f819.yaml
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Co-authored-by: Matthew Treinish <mtreinish@kortar.org>
Previously, Hypothesis spent most of the test cycles adding
registers rather than useful instructions, and would in
fact skip running the equivalence test rule altogether,
so we'd pretty much expect testing to pass no matter
what.
This commit limits the number of classical and quantum
registers to 3 each (arbitrary) to increase the chances
of gate generation and invocation of the equivalence
transpilation rule.
The number of examples has also been increased from 25
to 200, which should vastly improve the coverage of
this test, at the expense of a longer runtime.
* Add VF2PostLayout pass
This commit adds a new transpiler VF2PostLayout and adds a new
phase/model to the preset transpiler pipeline post-layout/qubit
selection. The idea is based on the mapomatic project [1] which
took the code from the existing VF2Layout pass to find an isomorphic
subgraph in the coupling graph after transpilation which had better
noise characteristics than those initial selected as part of the initial
layout phase. Doing post transpile qubit selection provides the pass
more information because we can assume that the circuit's operations are
in the target basis and that there is at least 1 subgraph already in the
coupling graph because we've gone through routing. This enables us to
look at the specific error rates for each instruction and weigh the sum
of error rates for the mapped circuit on each potential qubit mapping to
find the best performing set of qubits for a given circuit. Initial
layout doesn't have access to this information because at the beginning
of the circuit we aren't necessarily going to find a perfect mapping and
we're not guaranteed to be in the target basis. So running post layout
may yield quality improvements even if we found an initial perfect
layout using VF2Layout.
While this new pass is very similar to VF2Layout pass as it builds an
interaction graph representing the 2q interactions in the circuit and
uses retworkx's vf2_mapping() function to find all isomorphic subgraphs
in the coupling graph it behaves diffferently. This is a separate pass
because it performs the search a bit differently. First the interaction
graphs are annotated with the gate counts on each qubit and edge which
is used to completely apply a heuristic score to the circuit and secondly
in the case of a target we verify the nodes and edges are feasible in the
subgraph isomorphism check since a target can have operations defined on
a subset of bits. Additionally the scoring heursitic checks the
sum of the error rates for each gate on the mapped qubits.
The preset pass managers are updated to use this new pass at the end of
the transpile and apply a layout if a solution is found.
[1] https://github.com/Qiskit-Partners/mapomatic
* Fix matching callback function
The matching callback function had a typo so it was always returning
True on edge comparisons even if the target coupling graph edge was not
a superset of the local gates in the interaction graph. This commit
fixes the oversight so such cases are correctly rejected as a viable
subgraph isomorphic graph.
* Fix lint
* Add back removed ancillas to layout
If we find a a better layout using post layout and there are ancillas in
the original layout those would previously be lost. This commit fixes
this by detecting when we're missing qubits in the new layout and adding
the ancillas on unused qubits in the coupling graph.
* Move VF2PostLayout before scheduling
Applying a new layout after we schedule a circuit would invalidate
that scheduling. This commit moves the post layout pass to run prior
to scheduling in the preset passmanagers.
* Fix docs
* Drop max_trials and rely solely on time
* Fix ancilla handling
* Restore original virtual bits and registers
This commit modifies the ApplyLayout pass to enable slightly altered
behavior when applying a post layout ontop of a circuit that's already
had a layout applied. Previously we overwrote the layout and apply
layout just blindly applied the layout, this caused us to lose the
original bit and register context as that only exists as metadata
in the property set's layout field. To ensure we preserve the mapping
from the initial virtual bits through our second round of layout apply
layout is modified to handle doing this mapping for us by passing the
new layout separately as a new field in the property set.
* Only run post layout if no manual layout options are set
If initial_layout or layout_method are set in transpile() do not run
post layout as this will produce unexpected results for users. If you're
manually specifying a layout method that should be what is used only and
we shouldn't do any other reordering to try and optimize beyond what the
user requested.
* Only run VF2PostLayout if there are connectivity constraints in the target
* Adjust cost function to no be a sum of error rates
* Update tests that check exact layout
After introducing VF2PostLayout the output layout of the circuit is
potentially different depending on the noise characteristics of the
target backend. This was causing test failures on tests that were
explicitly checking for an exact layout output from transpile. This
commit updates the expected layouts in those tests to match the new
behavior of the transpiler. Most of these tests were actually already
using VF2Layout to find a perfect layout, but with vf2layout the
transpiler is finding an alternative layout post optimization which has
better noise characteristics for the circuit being run.
* Fix lint
* Fix typo in target node/edge match function
This commit fixes a typo in the node/edge match function used in
matching a subgraph to a target over valid operation names. Previously
the reverse condition check was incorrectly checking that the target
operations on a 2q edge were a subset of the circuit operations when it
should have been checking the reverse condition. This commit fixes this
oversight.
* Add release notes
* Add tests
* Update release notes
* Fix typos in release notes
Co-authored-by: Ali Javadi-Abhari <ajavadia@users.noreply.github.com>
* Add strict_direction flag to pass
This commit adds a new flag, strict_direction, which can be used to do
an isomorphic match on undirected graphs and use an avg 1q and 2q error
rate for each qubit for scoring.
* Move VF2PostLayout to right after routing in preset passmanagers
This commit moves the VF2PostLayout run to right after the routing phase
in the preset passmanagers. This lets us set the strict_direction flag
to False which expands the search space to ignore 2q gate
directionality which will potentially find better mappings.
* Updated expected test layout for v2 failing test case
* Fix doc issues
Co-authored-by: Ali Javadi-Abhari <ajavadia@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* change adjoining_run logic
* change insert to append and remove assertion
* use deque to optimize deletion
* remove copy and change condition
* add deque for commuted
This commit updates the strategies used to do the randomised testing of
transpiler equivalence, having three main effects:
1. The "pre-transpilation" circuit is now run on an Aer backend without
any transpilation at all, making the test truer to its name.
Previously `execute` was used which secretly performs a transpilation
internally. This was accompanied by a small change to the set of
gates, to ensure only those that are directly supported by Aer are
used.
2. The strategies used for drawing gates are simplified into (mostly) a
single rule that draws a gate from a set, and populates it. This is
just tidying up - it unifies the logic for drawing a gate into one
strategy rather than several.
3. The tests are updated to avoid using deprecated behaviour (e.g.
back-referencing a register from a bit) or features (e.g. various old
gate classes, and the old Aer `qasm_simulator`).
Point 1 in this list is also a fix to recent randomised testing
failures; since the tests were updated in ff4ee1b to call `backend.run`
directly (rather than `execute`) in the second run of each circuit,
when Hypothesis was drawing `None` as the backend in conjunction with a
gate Aer didn't know how to simulate (e.g. `CRZGate`), Aer would raise
an exception. Previously this behaviour was hidden by the internal call
to `transpile` inherent in `execute`, and was a logic error in the test
suite, rather than in Terra.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Pradeep Krishnamurthy