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Fix circuit drawer returning qubit[register] names for input (#11096)
* added registers to layout in sabre_layout pass * Add reno and test * Fix layout method in test * Set transpiler seed * modified reference circuit for test --------- Co-authored-by: Elena Peña Tapia <epenatap@gmail.com> Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com>
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@ -279,6 +279,10 @@ class SabreLayout(TransformationPass):
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}
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)
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# Add the existing registers to the layout
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for qreg in dag.qregs.values():
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self.property_set["layout"].add_register(qreg)
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# If skip_routing is set then return the layout in the property set
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# and throwaway the extra work we did to compute the swap map.
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# We also skip routing here if there is more than one connected
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@ -0,0 +1,8 @@
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---
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fixes:
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- |
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Fixed a bug in :class:`~.SabreLayout` where it would fail to add the layout
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register information to the property set. This affected circuit visualization, as
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``circuit.draw()`` after transpilation with certain optimization levels would show
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the full ``Qubit[register]`` label rather than the expected register name
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(e.g. ``q0``).
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@ -1,6 +1,6 @@
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# This code is part of Qiskit.
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#
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# (C) Copyright IBM 2020.
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# (C) Copyright IBM 2020, 2023.
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#
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# This code is licensed under the Apache License, Version 2.0. You may
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# obtain a copy of this license in the LICENSE.txt file in the root directory
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@ -2177,6 +2177,7 @@ class TestCircuitMatplotlibDrawer(QiskitTestCase):
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backend.target.add_instruction(SwitchCaseOp, name="switch_case")
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backend.target.add_instruction(IfElseOp, name="if_else")
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tqc = transpile(qc, backend, optimization_level=2, seed_transpiler=671_42)
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fname = "nested_layout_control_flow.png"
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self.circuit_drawer(tqc, output="mpl", filename=fname)
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@ -2208,6 +2209,31 @@ class TestCircuitMatplotlibDrawer(QiskitTestCase):
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):
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qc.draw("mpl", style=style)
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def test_no_qreg_names_after_layout(self):
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"""Test that full register names are not shown after transpilation.
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See https://github.com/Qiskit/qiskit-terra/issues/11038"""
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backend = FakeBelemV2()
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qc = QuantumCircuit(3)
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qc.cx(0, 1)
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qc.cx(1, 2)
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qc.cx(2, 0)
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circuit = transpile(
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qc, backend, basis_gates=["rz", "sx", "cx"], layout_method="sabre", seed_transpiler=42
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)
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fname = "qreg_names_after_layout.png"
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self.circuit_drawer(circuit, output="mpl", filename=fname)
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ratio = VisualTestUtilities._save_diff(
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self._image_path(fname),
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self._reference_path(fname),
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fname,
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FAILURE_DIFF_DIR,
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FAILURE_PREFIX,
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)
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self.assertGreaterEqual(ratio, 0.9999)
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if __name__ == "__main__":
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unittest.main(verbosity=1)
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