Fix circuit drawer returning qubit[register] names for input (#11096)

* added registers to layout in sabre_layout pass

* Add reno and test

* Fix layout method in test

* Set transpiler seed

* modified reference circuit for test

---------

Co-authored-by: Elena Peña Tapia <epenatap@gmail.com>
Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com>
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SoranaAurelia 2023-11-06 11:50:20 +02:00 committed by GitHub
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4 changed files with 39 additions and 1 deletions

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@ -279,6 +279,10 @@ class SabreLayout(TransformationPass):
}
)
# Add the existing registers to the layout
for qreg in dag.qregs.values():
self.property_set["layout"].add_register(qreg)
# If skip_routing is set then return the layout in the property set
# and throwaway the extra work we did to compute the swap map.
# We also skip routing here if there is more than one connected

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@ -0,0 +1,8 @@
---
fixes:
- |
Fixed a bug in :class:`~.SabreLayout` where it would fail to add the layout
register information to the property set. This affected circuit visualization, as
``circuit.draw()`` after transpilation with certain optimization levels would show
the full ``Qubit[register]`` label rather than the expected register name
(e.g. ``q0``).

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@ -1,6 +1,6 @@
# This code is part of Qiskit.
#
# (C) Copyright IBM 2020.
# (C) Copyright IBM 2020, 2023.
#
# This code is licensed under the Apache License, Version 2.0. You may
# obtain a copy of this license in the LICENSE.txt file in the root directory
@ -2177,6 +2177,7 @@ class TestCircuitMatplotlibDrawer(QiskitTestCase):
backend.target.add_instruction(SwitchCaseOp, name="switch_case")
backend.target.add_instruction(IfElseOp, name="if_else")
tqc = transpile(qc, backend, optimization_level=2, seed_transpiler=671_42)
fname = "nested_layout_control_flow.png"
self.circuit_drawer(tqc, output="mpl", filename=fname)
@ -2208,6 +2209,31 @@ class TestCircuitMatplotlibDrawer(QiskitTestCase):
):
qc.draw("mpl", style=style)
def test_no_qreg_names_after_layout(self):
"""Test that full register names are not shown after transpilation.
See https://github.com/Qiskit/qiskit-terra/issues/11038"""
backend = FakeBelemV2()
qc = QuantumCircuit(3)
qc.cx(0, 1)
qc.cx(1, 2)
qc.cx(2, 0)
circuit = transpile(
qc, backend, basis_gates=["rz", "sx", "cx"], layout_method="sabre", seed_transpiler=42
)
fname = "qreg_names_after_layout.png"
self.circuit_drawer(circuit, output="mpl", filename=fname)
ratio = VisualTestUtilities._save_diff(
self._image_path(fname),
self._reference_path(fname),
fname,
FAILURE_DIFF_DIR,
FAILURE_PREFIX,
)
self.assertGreaterEqual(ratio, 0.9999)
if __name__ == "__main__":
unittest.main(verbosity=1)