359 lines
11 KiB
C
359 lines
11 KiB
C
/* sim-safe.c - sample functional simulator implementation */
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/* SimpleScalar(TM) Tool Suite
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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* All Rights Reserved.
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*
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* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
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* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
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*
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* No portion of this work may be used by any commercial entity, or for any
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* commercial purpose, without the prior, written permission of SimpleScalar,
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* LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
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* as described below.
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*
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* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
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* or implied. The user of the program accepts full responsibility for the
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* application of the program and the use of any results.
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*
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* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
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* downloaded, compiled, executed, copied, and modified solely for nonprofit,
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* educational, noncommercial research, and noncommercial scholarship
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* purposes provided that this notice in its entirety accompanies all copies.
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* Copies of the modified software can be delivered to persons who use it
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* solely for nonprofit, educational, noncommercial research, and
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* noncommercial scholarship purposes provided that this notice in its
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* entirety accompanies all copies.
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*
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* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
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* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
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*
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* 4. No nonprofit user may place any restrictions on the use of this software,
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* including as modified by the user, by any other authorized user.
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*
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* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
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* in compiled or executable form as set forth in Section 2, provided that
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* either: (A) it is accompanied by the corresponding machine-readable source
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* code, or (B) it is accompanied by a written offer, with no time limit, to
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* give anyone a machine-readable copy of the corresponding source code in
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* return for reimbursement of the cost of distribution. This written offer
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* must permit verbatim duplication by anyone, or (C) it is distributed by
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* someone who received only the executable form, and is accompanied by a
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* copy of the written offer of source code.
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*
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* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
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* currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
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* 2395 Timbercrest Court, Ann Arbor, MI 48105.
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*
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include "host.h"
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#include "misc.h"
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#include "machine.h"
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#include "regs.h"
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#include "memory.h"
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#include "loader.h"
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#include "syscall.h"
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#include "dlite.h"
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#include "options.h"
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#include "stats.h"
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#include "sim.h"
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/*
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* This file implements a functional simulator. This functional simulator is
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* the simplest, most user-friendly simulator in the simplescalar tool set.
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* Unlike sim-fast, this functional simulator checks for all instruction
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* errors, and the implementation is crafted for clarity rather than speed.
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*/
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/* simulated registers */
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static struct regs_t regs;
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/* simulated memory */
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static struct mem_t *mem = NULL;
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/* track number of refs */
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static counter_t sim_num_refs = 0;
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/* maximum number of inst's to execute */
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static unsigned int max_insts;
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/* register simulator-specific options */
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void
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sim_reg_options(struct opt_odb_t *odb)
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{
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opt_reg_header(odb,
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"sim-safe: This simulator implements a functional simulator. This\n"
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"functional simulator is the simplest, most user-friendly simulator in the\n"
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"simplescalar tool set. Unlike sim-fast, this functional simulator checks\n"
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"for all instruction errors, and the implementation is crafted for clarity\n"
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"rather than speed.\n"
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);
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/* instruction limit */
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opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
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&max_insts, /* default */0,
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/* print */TRUE, /* format */NULL);
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}
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/* check simulator-specific option values */
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void
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sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
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{
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/* nada */
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}
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/* register simulator-specific statistics */
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void
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sim_reg_stats(struct stat_sdb_t *sdb)
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{
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stat_reg_counter(sdb, "sim_num_insn",
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"total number of instructions executed",
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&sim_num_insn, sim_num_insn, NULL);
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stat_reg_counter(sdb, "sim_num_refs",
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"total number of loads and stores executed",
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&sim_num_refs, 0, NULL);
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stat_reg_int(sdb, "sim_elapsed_time",
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"total simulation time in seconds",
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&sim_elapsed_time, 0, NULL);
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stat_reg_formula(sdb, "sim_inst_rate",
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"simulation speed (in insts/sec)",
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"sim_num_insn / sim_elapsed_time", NULL);
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ld_reg_stats(sdb);
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mem_reg_stats(mem, sdb);
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}
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/* initialize the simulator */
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void
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sim_init(void)
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{
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sim_num_refs = 0;
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/* allocate and initialize register file */
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regs_init(®s);
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/* allocate and initialize memory space */
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mem = mem_create("mem");
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mem_init(mem);
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}
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/* load program into simulated state */
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void
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sim_load_prog(char *fname, /* program to load */
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int argc, char **argv, /* program arguments */
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char **envp) /* program environment */
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{
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/* load program text and data, set up environment, memory, and regs */
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ld_load_prog(fname, argc, argv, envp, ®s, mem, TRUE);
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/* initialize the DLite debugger */
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dlite_init(md_reg_obj, dlite_mem_obj, dlite_mstate_obj);
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}
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/* print simulator-specific configuration information */
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void
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sim_aux_config(FILE *stream) /* output stream */
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{
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/* nothing currently */
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}
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/* dump simulator-specific auxiliary simulator statistics */
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void
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sim_aux_stats(FILE *stream) /* output stream */
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{
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/* nada */
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}
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/* un-initialize simulator-specific state */
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void
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sim_uninit(void)
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{
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/* nada */
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}
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/*
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* configure the execution engine
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*/
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/*
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* precise architected register accessors
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*/
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/* next program counter */
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#define SET_NPC(EXPR) (regs.regs_NPC = (EXPR))
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/* current program counter */
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#define CPC (regs.regs_PC)
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/* general purpose registers */
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#define GPR(N) (regs.regs_R[N])
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#define SET_GPR(N,EXPR) (regs.regs_R[N] = (EXPR))
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#if defined(TARGET_PISA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_L(N) (regs.regs_F.l[(N)])
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#define SET_FPR_L(N,EXPR) (regs.regs_F.l[(N)] = (EXPR))
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#define FPR_F(N) (regs.regs_F.f[(N)])
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#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))
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#define FPR_D(N) (regs.regs_F.d[(N) >> 1])
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#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = (EXPR))
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/* miscellaneous register accessors */
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#define SET_HI(EXPR) (regs.regs_C.hi = (EXPR))
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#define HI (regs.regs_C.hi)
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#define SET_LO(EXPR) (regs.regs_C.lo = (EXPR))
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#define LO (regs.regs_C.lo)
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#define FCC (regs.regs_C.fcc)
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#define SET_FCC(EXPR) (regs.regs_C.fcc = (EXPR))
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#elif defined(TARGET_ALPHA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_Q(N) (regs.regs_F.q[N])
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#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[N] = (EXPR))
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#define FPR(N) (regs.regs_F.d[(N)])
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#define SET_FPR(N,EXPR) (regs.regs_F.d[(N)] = (EXPR))
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/* miscellaneous register accessors */
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#define FPCR (regs.regs_C.fpcr)
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#define SET_FPCR(EXPR) (regs.regs_C.fpcr = (EXPR))
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#define UNIQ (regs.regs_C.uniq)
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#define SET_UNIQ(EXPR) (regs.regs_C.uniq = (EXPR))
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#else
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#error No ISA target defined...
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#endif
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/* precise architected memory state accessor macros */
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#define READ_BYTE(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_BYTE(mem, addr))
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#define READ_HALF(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_HALF(mem, addr))
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#define READ_WORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_WORD(mem, addr))
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#ifdef HOST_HAS_QWORD
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#define READ_QWORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_QWORD(mem, addr))
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#endif /* HOST_HAS_QWORD */
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#define WRITE_BYTE(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_BYTE(mem, addr, (SRC)))
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#define WRITE_HALF(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_HALF(mem, addr, (SRC)))
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#define WRITE_WORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_WORD(mem, addr, (SRC)))
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#ifdef HOST_HAS_QWORD
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#define WRITE_QWORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_QWORD(mem, addr, (SRC)))
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#endif /* HOST_HAS_QWORD */
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/* system call handler macro */
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#define SYSCALL(INST) sys_syscall(®s, mem_access, mem, INST, TRUE)
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/* start simulation, program loaded, processor precise state initialized */
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void
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sim_main(void)
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{
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md_inst_t inst;
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register md_addr_t addr;
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enum md_opcode op;
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register int is_write;
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enum md_fault_type fault;
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fprintf(stderr, "sim: ** starting functional simulation **\n");
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/* set up initial default next PC */
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regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
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/* check for DLite debugger entry condition */
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if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
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dlite_main(regs.regs_PC - sizeof(md_inst_t),
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regs.regs_PC, sim_num_insn, ®s, mem);
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while (TRUE)
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{
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/* maintain $r0 semantics */
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regs.regs_R[MD_REG_ZERO] = 0;
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#ifdef TARGET_ALPHA
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regs.regs_F.d[MD_REG_ZERO] = 0.0;
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#endif /* TARGET_ALPHA */
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/* get the next instruction to execute */
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MD_FETCH_INST(inst, mem, regs.regs_PC);
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/* keep an instruction count */
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sim_num_insn++;
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/* set default reference address and access mode */
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addr = 0; is_write = FALSE;
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/* set default fault - none */
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fault = md_fault_none;
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/* decode the instruction */
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MD_SET_OPCODE(op, inst);
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/* execute the instruction */
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switch (op)
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{
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#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
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case OP: \
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SYMCAT(OP,_IMPL); \
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break;
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#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
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case OP: \
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panic("attempted to execute a linking opcode");
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#define CONNECT(OP)
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#define DECLARE_FAULT(FAULT) \
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{ fault = (FAULT); break; }
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#include "machine.def"
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default:
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panic("attempted to execute a bogus opcode");
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}
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if (fault != md_fault_none)
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fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
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if (verbose)
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{
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myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
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sim_num_insn, md_xor_regs(®s), regs.regs_PC);
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md_print_insn(inst, regs.regs_PC, stderr);
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if (MD_OP_FLAGS(op) & F_MEM)
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myfprintf(stderr, " mem: 0x%08p", addr);
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fprintf(stderr, "\n");
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/* fflush(stderr); */
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}
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if (MD_OP_FLAGS(op) & F_MEM)
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{
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sim_num_refs++;
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if (MD_OP_FLAGS(op) & F_STORE)
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is_write = TRUE;
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}
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/* check for DLite debugger entry condition */
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if (dlite_check_break(regs.regs_NPC,
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is_write ? ACCESS_WRITE : ACCESS_READ,
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addr, sim_num_insn, sim_num_insn))
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dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
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/* go to the next instruction */
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regs.regs_PC = regs.regs_NPC;
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regs.regs_NPC += sizeof(md_inst_t);
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/* finish early? */
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if (max_insts && sim_num_insn >= max_insts)
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return;
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}
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}
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