603 lines
18 KiB
C
603 lines
18 KiB
C
/* sim-eio.c - external I/O trace generator */
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/* SimpleScalar(TM) Tool Suite
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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* All Rights Reserved.
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*
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* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
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* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
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*
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* No portion of this work may be used by any commercial entity, or for any
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* commercial purpose, without the prior, written permission of SimpleScalar,
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* LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
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* as described below.
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*
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* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
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* or implied. The user of the program accepts full responsibility for the
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* application of the program and the use of any results.
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*
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* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
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* downloaded, compiled, executed, copied, and modified solely for nonprofit,
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* educational, noncommercial research, and noncommercial scholarship
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* purposes provided that this notice in its entirety accompanies all copies.
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* Copies of the modified software can be delivered to persons who use it
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* solely for nonprofit, educational, noncommercial research, and
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* noncommercial scholarship purposes provided that this notice in its
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* entirety accompanies all copies.
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*
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* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
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* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
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*
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* 4. No nonprofit user may place any restrictions on the use of this software,
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* including as modified by the user, by any other authorized user.
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*
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* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
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* in compiled or executable form as set forth in Section 2, provided that
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* either: (A) it is accompanied by the corresponding machine-readable source
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* code, or (B) it is accompanied by a written offer, with no time limit, to
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* give anyone a machine-readable copy of the corresponding source code in
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* return for reimbursement of the cost of distribution. This written offer
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* must permit verbatim duplication by anyone, or (C) it is distributed by
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* someone who received only the executable form, and is accompanied by a
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* copy of the written offer of source code.
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*
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* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
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* currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
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* 2395 Timbercrest Court, Ann Arbor, MI 48105.
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*
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include "host.h"
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#include "misc.h"
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#include "machine.h"
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#include "regs.h"
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#include "memory.h"
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#include "loader.h"
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#include "syscall.h"
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#include "dlite.h"
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#include "options.h"
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#include "stats.h"
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#include "eio.h"
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#include "range.h"
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#include "sim.h"
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/*
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* This file implements a functional simulator. This functional simulator is
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* the simplest, most user-friendly simulator in the simplescalar tool set.
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* Unlike sim-fast, this functional simulator checks for all instruction
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* errors, and the implementation is crafted for clarity rather than speed.
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*/
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/* simulated registers */
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static struct regs_t regs;
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/* simulated memory */
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static struct mem_t *mem = NULL;
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/* track number of refs */
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static counter_t sim_num_refs = 0;
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/* maximum number of inst's to execute */
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static unsigned int max_insts;
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/* number of insts skipped before timing starts */
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static int fastfwd_count;
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/* non-zero when fastforward'ing */
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static int fastfwding = FALSE;
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/* external I/O filename */
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static char *trace_fname;
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static FILE *trace_fd = NULL;
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/* checkpoint filename and file descriptor */
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static enum { no_chkpt, one_shot_chkpt, periodic_chkpt } chkpt_kind = no_chkpt;
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static char *chkpt_fname;
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static FILE *chkpt_fd = NULL;
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static struct range_range_t chkpt_range;
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/* periodic checkpoint args */
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static counter_t per_chkpt_interval;
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static counter_t next_chkpt_cycle;
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static unsigned int chkpt_num;
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/* checkpoint output filename and range */
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static int chkpt_nelt = 0;
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static char *chkpt_opts[2];
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/* periodic checkpoint output filename and range */
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static int per_chkpt_nelt = 0;
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static char *per_chkpt_opts[2];
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/* register simulator-specific options */
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void
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sim_reg_options(struct opt_odb_t *odb)
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{
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opt_reg_header(odb,
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"sim-eio: This simulator implements simulator support for generating\n"
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"external event traces (EIO traces) and checkpoint files. External\n"
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"event traces capture one execution of a program, and allow it to be\n"
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"packaged into a single file for later re-execution. EIO trace executions\n"
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"are 100% reproducible between subsequent executions (on the same platform.\n"
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"This simulator also provides functionality to generate checkpoints at\n"
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"arbitrary points within an external event trace (EIO) execution. The\n"
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"checkpoint file (along with the EIO trace) can be used to start any\n"
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"SimpleScalar simulator in the middle of a program execution.\n"
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);
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/* instruction limit */
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opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
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&max_insts, /* default */0,
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/* print */TRUE, /* format */NULL);
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opt_reg_int(odb, "-fastfwd", "number of insts skipped before tracing starts",
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&fastfwd_count, /* default */0,
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/* print */TRUE, /* format */NULL);
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opt_reg_string(odb, "-trace", "EIO trace file output file name",
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&trace_fname, /* default */NULL,
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/* print */TRUE, NULL);
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opt_reg_string_list(odb, "-perdump",
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"periodic checkpoint every n instructions: "
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"<base fname> <interval>",
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per_chkpt_opts, /* sz */2, &per_chkpt_nelt,
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/* default */NULL,
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/* !print */FALSE, /* format */NULL, /* !accrue */FALSE);
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opt_reg_string_list(odb, "-dump",
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"specify checkpoint file and trigger: <fname> <range>",
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chkpt_opts, /* sz */2, &chkpt_nelt, /* default */NULL,
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/* !print */FALSE, /* format */NULL, /* !accrue */FALSE);
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opt_reg_note(odb,
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" Checkpoint range triggers are formatted as follows:\n"
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"\n"
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" {{@|#}<start>}:{{@|#|+}<end>}\n"
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"\n"
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" Both ends of the range are optional, if neither are specified, the range\n"
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" triggers immediately. Ranges that start with a `@' designate an address\n"
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" range to trigger on, those that start with an `#' designate a cycle count\n"
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" trigger. All other ranges represent an instruction count range. The\n"
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" second argument, if specified with a `+', indicates a value relative\n"
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" to the first argument, e.g., 1000:+100 == 1000:1100.\n"
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"\n"
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" Examples: -ptrace FOO.trc #0:#1000\n"
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" -ptrace BAR.trc @2000:\n"
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" -ptrace BLAH.trc :1500\n"
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" -ptrace UXXE.trc :\n"
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);
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}
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/* check simulator-specific option values */
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void
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sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
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{
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if (fastfwd_count < 0 || fastfwd_count >= 2147483647)
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fatal("bad fast forward count: %d", fastfwd_count);
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}
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/* register simulator-specific statistics */
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void
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sim_reg_stats(struct stat_sdb_t *sdb)
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{
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stat_reg_counter(sdb, "sim_num_insn",
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"total number of instructions executed",
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&sim_num_insn, sim_num_insn, NULL);
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stat_reg_counter(sdb, "sim_num_refs",
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"total number of loads and stores executed",
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&sim_num_refs, 0, NULL);
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stat_reg_int(sdb, "sim_elapsed_time",
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"total simulation time in seconds",
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&sim_elapsed_time, 0, NULL);
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stat_reg_formula(sdb, "sim_inst_rate",
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"simulation speed (in insts/sec)",
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"sim_num_insn / sim_elapsed_time", NULL);
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ld_reg_stats(sdb);
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mem_reg_stats(mem, sdb);
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}
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/* initialize the simulator */
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void
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sim_init(void)
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{
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sim_num_refs = 0;
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/* allocate and initialize register file */
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regs_init(®s);
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/* allocate and initialize memory space */
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mem = mem_create("mem");
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mem_init(mem);
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}
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/* load program into simulated state */
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void
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sim_load_prog(char *fname, /* program to load */
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int argc, char **argv, /* program arguments */
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char **envp) /* program environment */
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{
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/* load program text and data, set up environment, memory, and regs */
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ld_load_prog(fname, argc, argv, envp, ®s, mem, TRUE);
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if (chkpt_nelt == 2)
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{
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char *errstr;
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/* generate a checkpoint */
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if (!sim_eio_fd)
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fatal("checkpoints can only be generated while running an EIO trace");
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/* can't do regular & periodic chkpts at the same time */
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if (per_chkpt_nelt != 0)
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fatal("can't do both regular and periodic checkpoints");
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#if 0 /* this should work fine... */
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if (trace_fname != NULL)
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fatal("checkpoints cannot be generated with generating an EIO trace");
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#endif
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/* parse the range */
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errstr = range_parse_range(chkpt_opts[1], &chkpt_range);
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if (errstr)
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fatal("cannot parse pipetrace range, use: {<start>}:{<end>}");
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/* create the checkpoint file */
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chkpt_fname = chkpt_opts[0];
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chkpt_fd = eio_create(chkpt_fname);
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/* indicate checkpointing is now active... */
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chkpt_kind = one_shot_chkpt;
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}
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if (per_chkpt_nelt == 2)
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{
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chkpt_fname = per_chkpt_opts[0];
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if (strchr(chkpt_fname, '%') == NULL)
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fatal("periodic checkpoint filename must be printf-style format");
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if (sscanf(per_chkpt_opts[1], "%Ld", &per_chkpt_interval) != 1)
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fatal("can't parse periodic checkpoint interval '%s'",
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per_chkpt_opts[1]);
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/* indicate checkpointing is now active... */
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chkpt_kind = periodic_chkpt;
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chkpt_num = 1;
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next_chkpt_cycle = per_chkpt_interval;
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}
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if (trace_fname != NULL)
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{
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fprintf(stderr, "sim: tracing execution to EIO file `%s'...\n",
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trace_fname);
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/* create an EIO trace file */
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trace_fd = eio_create(trace_fname);
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}
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/* initialize the DLite debugger */
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dlite_init(md_reg_obj, dlite_mem_obj, dlite_mstate_obj);
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}
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/* print simulator-specific configuration information */
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void
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sim_aux_config(FILE *stream) /* output stream */
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{
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/* nothing currently */
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}
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/* dump simulator-specific auxiliary simulator statistics */
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void
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sim_aux_stats(FILE *stream) /* output stream */
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{
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/* nada */
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}
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/* un-initialize simulator-specific state */
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void
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sim_uninit(void)
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{
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if (trace_fd != NULL)
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eio_close(trace_fd);
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}
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/*
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* configure the execution engine
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*/
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/*
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* precise architected register accessors
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*/
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/* next program counter */
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#define SET_NPC(EXPR) (regs.regs_NPC = (EXPR))
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/* current program counter */
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#define CPC (regs.regs_PC)
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/* general purpose registers */
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#define GPR(N) (regs.regs_R[N])
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#define SET_GPR(N,EXPR) (regs.regs_R[N] = (EXPR))
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#if defined(TARGET_PISA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_L(N) (regs.regs_F.l[(N)])
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#define SET_FPR_L(N,EXPR) (regs.regs_F.l[(N)] = (EXPR))
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#define FPR_F(N) (regs.regs_F.f[(N)])
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#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))
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#define FPR_D(N) (regs.regs_F.d[(N) >> 1])
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#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = (EXPR))
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/* miscellaneous register accessors */
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#define SET_HI(EXPR) (regs.regs_C.hi = (EXPR))
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#define HI (regs.regs_C.hi)
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#define SET_LO(EXPR) (regs.regs_C.lo = (EXPR))
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#define LO (regs.regs_C.lo)
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#define FCC (regs.regs_C.fcc)
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#define SET_FCC(EXPR) (regs.regs_C.fcc = (EXPR))
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#elif defined(TARGET_ALPHA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_Q(N) (regs.regs_F.q[N])
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#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[N] = (EXPR))
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#define FPR(N) (regs.regs_F.d[N])
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#define SET_FPR(N,EXPR) (regs.regs_F.d[N] = (EXPR))
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/* miscellaneous register accessors */
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#define FPCR (regs.regs_C.fpcr)
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#define SET_FPCR(EXPR) (regs.regs_C.fpcr = (EXPR))
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#define UNIQ (regs.regs_C.uniq)
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#define SET_UNIQ(EXPR) (regs.regs_C.uniq = (EXPR))
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#else
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#error No ISA target defined...
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#endif
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/* precise architected memory state accessor macros */
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#define READ_BYTE(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_BYTE(mem, addr))
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#define READ_HALF(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_HALF(mem, addr))
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#define READ_WORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_WORD(mem, addr))
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#ifdef HOST_HAS_QWORD
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#define READ_QWORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_QWORD(mem, addr))
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#endif /* HOST_HAS_QWORD */
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#define WRITE_BYTE(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_BYTE(mem, addr, (SRC)))
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#define WRITE_HALF(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_HALF(mem, addr, (SRC)))
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#define WRITE_WORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_WORD(mem, addr, (SRC)))
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#ifdef HOST_HAS_QWORD
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#define WRITE_QWORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_QWORD(mem, addr, (SRC)))
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#endif /* HOST_HAS_QWORD */
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/* system call handler macro */
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#define SYSCALL(INST) \
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((trace_fd != NULL && !fastfwding) \
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? eio_write_trace(trace_fd, sim_num_insn, \
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®s, mem_access, mem, INST) \
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: sys_syscall(®s, mem_access, mem, INST, TRUE))
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/* start simulation, program loaded, processor precise state initialized */
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void
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sim_main(void)
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{
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md_inst_t inst;
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register md_addr_t addr;
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enum md_opcode op;
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register bool_t is_write;
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enum md_fault_type fault;
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/* set up initial default next PC */
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regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
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/* check for DLite debugger entry condition */
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if (dlite_check_break(regs.regs_PC, /* !access */0, /* addr */0, 0, 0))
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dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
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sim_num_insn, ®s, mem);
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/* fast forward simulator loop, performs functional simulation for
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FASTFWD_COUNT insts, then turns on performance (timing) simulation */
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if (fastfwd_count > 0)
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{
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int icount;
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fprintf(stderr, "sim: ** fast forwarding %d insts **\n", fastfwd_count);
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fastfwding = TRUE;
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for (icount=0; icount < fastfwd_count; icount++)
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{
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/* maintain $r0 semantics */
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regs.regs_R[MD_REG_ZERO] = 0;
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#ifdef TARGET_ALPHA
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regs.regs_F.d[MD_REG_ZERO] = 0.0;
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#endif /* TARGET_ALPHA */
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/* get the next instruction to execute */
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MD_FETCH_INST(inst, mem, regs.regs_PC);
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/* set default reference address */
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addr = 0; is_write = FALSE;
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/* set default fault - none */
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fault = md_fault_none;
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/* decode the instruction */
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MD_SET_OPCODE(op, inst);
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/* execute the instruction */
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switch (op)
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{
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#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
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case OP: \
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SYMCAT(OP,_IMPL); \
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break;
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#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
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case OP: \
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panic("attempted to execute a linking opcode");
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#define CONNECT(OP)
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#undef DECLARE_FAULT
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#define DECLARE_FAULT(FAULT) \
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{ fault = (FAULT); break; }
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#include "machine.def"
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default:
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panic("attempted to execute a bogus opcode");
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}
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if (fault != md_fault_none)
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fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
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/* update memory access stats */
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if (MD_OP_FLAGS(op) & F_MEM)
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{
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if (MD_OP_FLAGS(op) & F_STORE)
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is_write = TRUE;
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}
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/* check for DLite debugger entry condition */
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if (dlite_check_break(regs.regs_NPC,
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is_write ? ACCESS_WRITE : ACCESS_READ,
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addr, sim_num_insn, sim_num_insn))
|
|
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
|
|
|
|
/* go to the next instruction */
|
|
regs.regs_PC = regs.regs_NPC;
|
|
regs.regs_NPC += sizeof(md_inst_t);
|
|
}
|
|
}
|
|
fastfwding = FALSE;
|
|
|
|
if (trace_fd != NULL)
|
|
{
|
|
fprintf(stderr, "sim: writing EIO file initial checkpoint...\n");
|
|
if (eio_write_chkpt(®s, mem, trace_fd) != -1)
|
|
panic("checkpoint code is broken");
|
|
}
|
|
|
|
fprintf(stderr, "sim: ** starting functional simulation **\n");
|
|
|
|
/* set up initial default next PC */
|
|
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
|
|
|
|
while (TRUE)
|
|
{
|
|
/* maintain $r0 semantics */
|
|
regs.regs_R[MD_REG_ZERO] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
regs.regs_F.d[MD_REG_ZERO] = 0.0;
|
|
#endif /* TARGET_ALPHA */
|
|
|
|
/* check if checkpoint should be generated here... */
|
|
if (chkpt_kind == one_shot_chkpt
|
|
&& !range_cmp_range1(&chkpt_range, regs.regs_NPC,
|
|
sim_num_insn, sim_num_insn))
|
|
{
|
|
myfprintf(stderr, "sim: writing checkpoint file `%s' @ inst %n...\n",
|
|
chkpt_fname, sim_num_insn);
|
|
|
|
/* write the checkpoint file */
|
|
eio_write_chkpt(®s, mem, chkpt_fd);
|
|
|
|
/* close the checkpoint file */
|
|
eio_close(chkpt_fd);
|
|
|
|
/* exit jumps to the target set in main() */
|
|
longjmp(sim_exit_buf, /* exitcode + fudge */0+1);
|
|
}
|
|
else if (chkpt_kind == periodic_chkpt
|
|
&& sim_num_insn == next_chkpt_cycle)
|
|
{
|
|
char this_chkpt_fname[256];
|
|
|
|
/* 'chkpt_fname' should be a printf format string */
|
|
sprintf(this_chkpt_fname, chkpt_fname, chkpt_num);
|
|
chkpt_fd = eio_create(this_chkpt_fname);
|
|
|
|
myfprintf(stderr, "sim: writing checkpoint file `%s' @ inst %n...\n",
|
|
this_chkpt_fname, sim_num_insn);
|
|
|
|
/* write the checkpoint file */
|
|
eio_write_chkpt(®s, mem, chkpt_fd);
|
|
|
|
/* close the checkpoint file */
|
|
eio_close(chkpt_fd);
|
|
|
|
chkpt_num++;
|
|
next_chkpt_cycle += per_chkpt_interval;
|
|
}
|
|
|
|
/* get the next instruction to execute */
|
|
MD_FETCH_INST(inst, mem, regs.regs_PC);
|
|
|
|
/* keep an instruction count */
|
|
sim_num_insn++;
|
|
|
|
/* set default reference address and access mode */
|
|
addr = 0; is_write = FALSE;
|
|
|
|
/* set default fault - none */
|
|
fault = md_fault_none;
|
|
|
|
/* decode the instruction */
|
|
MD_SET_OPCODE(op, inst);
|
|
|
|
/* execute the instruction */
|
|
switch (op)
|
|
{
|
|
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
|
|
case OP: \
|
|
SYMCAT(OP,_IMPL); \
|
|
break;
|
|
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
|
|
case OP: \
|
|
panic("attempted to execute a linking opcode");
|
|
#define CONNECT(OP)
|
|
#define DECLARE_FAULT(FAULT) \
|
|
{ fault = (FAULT); break; }
|
|
#include "machine.def"
|
|
default:
|
|
panic("bogus opcode");
|
|
}
|
|
|
|
if (fault != md_fault_none)
|
|
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
|
|
|
|
if (MD_OP_FLAGS(op) & F_MEM)
|
|
{
|
|
sim_num_refs++;
|
|
if (MD_OP_FLAGS(op) & F_STORE)
|
|
is_write = TRUE;
|
|
}
|
|
|
|
/* check for DLite debugger entry condition */
|
|
if (dlite_check_break(regs.regs_NPC,
|
|
is_write ? ACCESS_WRITE : ACCESS_READ,
|
|
addr, sim_num_insn, sim_num_insn))
|
|
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
|
|
|
|
/* go to the next instruction */
|
|
regs.regs_PC = regs.regs_NPC;
|
|
regs.regs_NPC += sizeof(md_inst_t);
|
|
|
|
/* finish early? */
|
|
if (max_insts && sim_num_insn >= max_insts)
|
|
return;
|
|
}
|
|
}
|