834 lines
27 KiB
C
834 lines
27 KiB
C
/* sim-cache.c - sample cache simulator implementation */
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/* SimpleScalar(TM) Tool Suite
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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* All Rights Reserved.
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*
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* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
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* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
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*
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* No portion of this work may be used by any commercial entity, or for any
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* commercial purpose, without the prior, written permission of SimpleScalar,
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* LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
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* as described below.
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*
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* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
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* or implied. The user of the program accepts full responsibility for the
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* application of the program and the use of any results.
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*
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* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
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* downloaded, compiled, executed, copied, and modified solely for nonprofit,
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* educational, noncommercial research, and noncommercial scholarship
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* purposes provided that this notice in its entirety accompanies all copies.
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* Copies of the modified software can be delivered to persons who use it
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* solely for nonprofit, educational, noncommercial research, and
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* noncommercial scholarship purposes provided that this notice in its
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* entirety accompanies all copies.
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*
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* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
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* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
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*
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* 4. No nonprofit user may place any restrictions on the use of this software,
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* including as modified by the user, by any other authorized user.
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*
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* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
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* in compiled or executable form as set forth in Section 2, provided that
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* either: (A) it is accompanied by the corresponding machine-readable source
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* code, or (B) it is accompanied by a written offer, with no time limit, to
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* give anyone a machine-readable copy of the corresponding source code in
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* return for reimbursement of the cost of distribution. This written offer
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* must permit verbatim duplication by anyone, or (C) it is distributed by
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* someone who received only the executable form, and is accompanied by a
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* copy of the written offer of source code.
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*
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* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
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* currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
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* 2395 Timbercrest Court, Ann Arbor, MI 48105.
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*
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <assert.h>
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#include "host.h"
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#include "misc.h"
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#include "machine.h"
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#include "regs.h"
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#include "memory.h"
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#include "cache.h"
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#include "loader.h"
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#include "syscall.h"
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#include "dlite.h"
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#include "sim.h"
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/*
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* This file implements a functional cache simulator. Cache statistics are
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* generated for a user-selected cache and TLB configuration, which may include
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* up to two levels of instruction and data cache (with any levels unified),
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* and one level of instruction and data TLBs. No timing information is
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* generated (hence the distinction, "functional" simulator).
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*/
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/* simulated registers */
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static struct regs_t regs;
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/* simulated memory */
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static struct mem_t *mem = NULL;
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/* track number of insn and refs */
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static counter_t sim_num_refs = 0;
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/* maximum number of inst's to execute */
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static unsigned int max_insts;
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/* level 1 instruction cache, entry level instruction cache */
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static struct cache_t *cache_il1 = NULL;
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/* level 1 instruction cache */
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static struct cache_t *cache_il2 = NULL;
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/* level 1 data cache, entry level data cache */
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static struct cache_t *cache_dl1 = NULL;
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/* level 2 data cache */
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static struct cache_t *cache_dl2 = NULL;
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/* instruction TLB */
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static struct cache_t *itlb = NULL;
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/* data TLB */
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static struct cache_t *dtlb = NULL;
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/* text-based stat profiles */
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#define MAX_PCSTAT_VARS 8
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static struct stat_stat_t *pcstat_stats[MAX_PCSTAT_VARS];
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static counter_t pcstat_lastvals[MAX_PCSTAT_VARS];
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static struct stat_stat_t *pcstat_sdists[MAX_PCSTAT_VARS];
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/* wedge all stat values into a counter_t */
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#define STATVAL(STAT) \
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((STAT)->sc == sc_int \
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? (counter_t)*((STAT)->variant.for_int.var) \
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: ((STAT)->sc == sc_uint \
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? (counter_t)*((STAT)->variant.for_uint.var) \
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: ((STAT)->sc == sc_counter \
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? *((STAT)->variant.for_counter.var) \
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: (panic("bad stat class"), 0))))
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/* l1 data cache l1 block miss handler function */
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static unsigned int /* latency of block access */
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dl1_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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if (cache_dl2)
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{
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/* access next level of data cache hierarchy */
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return cache_access(cache_dl2, cmd, baddr, NULL, bsize,
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/* now */now, /* pudata */NULL, /* repl addr */NULL);
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}
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else
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{
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/* access main memory, which is always done in the main simulator loop */
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return /* access latency, ignored */1;
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}
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}
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/* l2 data cache block miss handler function */
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static unsigned int /* latency of block access */
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dl2_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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/* this is a miss to the lowest level, so access main memory, which is
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always done in the main simulator loop */
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return /* access latency, ignored */1;
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}
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/* l1 inst cache l1 block miss handler function */
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static unsigned int /* latency of block access */
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il1_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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if (cache_il2)
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{
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/* access next level of inst cache hierarchy */
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return cache_access(cache_il2, cmd, baddr, NULL, bsize,
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/* now */now, /* pudata */NULL, /* repl addr */NULL);
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}
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else
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{
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/* access main memory, which is always done in the main simulator loop */
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return /* access latency, ignored */1;
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}
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}
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/* l2 inst cache block miss handler function */
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static unsigned int /* latency of block access */
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il2_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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/* this is a miss to the lowest level, so access main memory, which is
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always done in the main simulator loop */
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return /* access latency, ignored */1;
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}
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/* inst cache block miss handler function */
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static unsigned int /* latency of block access */
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itlb_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
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/* no real memory access, however, should have user data space attached */
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assert(phy_page_ptr);
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/* fake translation, for now... */
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*phy_page_ptr = 0;
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return /* access latency, ignored */1;
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}
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/* data cache block miss handler function */
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static unsigned int /* latency of block access */
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dtlb_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
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md_addr_t baddr, /* block address to access */
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int bsize, /* size of block to access */
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struct cache_blk_t *blk, /* ptr to block in upper level */
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tick_t now) /* time of access */
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{
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md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
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/* no real memory access, however, should have user data space attached */
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assert(phy_page_ptr);
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/* fake translation, for now... */
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*phy_page_ptr = 0;
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return /* access latency, ignored */1;
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}
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/* cache/TLB options */
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static char *cache_dl1_opt /* = "none" */;
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static char *cache_dl2_opt /* = "none" */;
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static char *cache_il1_opt /* = "none" */;
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static char *cache_il2_opt /* = "none" */;
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static char *itlb_opt /* = "none" */;
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static char *dtlb_opt /* = "none" */;
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static int flush_on_syscalls /* = FALSE */;
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static int compress_icache_addrs /* = FALSE */;
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/* text-based stat profiles */
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static int pcstat_nelt = 0;
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static char *pcstat_vars[MAX_PCSTAT_VARS];
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/* convert 64-bit inst text addresses to 32-bit inst equivalents */
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#ifdef TARGET_PISA
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#define IACOMPRESS(A) \
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(compress_icache_addrs ? ((((A) - ld_text_base) >> 1) + ld_text_base) : (A))
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#define ISCOMPRESS(SZ) \
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(compress_icache_addrs ? ((SZ) >> 1) : (SZ))
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#else /* !TARGET_PISA */
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#define IACOMPRESS(A) (A)
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#define ISCOMPRESS(SZ) (SZ)
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#endif /* TARGET_PISA */
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/* Registe simulator-specific options */
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void
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sim_reg_options(struct opt_odb_t *odb) /* options database */
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{
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opt_reg_header(odb,
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"sim-cache: This simulator implements a functional cache simulator. Cache\n"
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"statistics are generated for a user-selected cache and TLB configuration,\n"
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"which may include up to two levels of instruction and data cache (with any\n"
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"levels unified), and one level of instruction and data TLBs. No timing\n"
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"information is generated.\n"
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);
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/* instruction limit */
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opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
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&max_insts, /* default */0,
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/* print */TRUE, /* format */NULL);
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opt_reg_string(odb, "-cache:dl1",
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"l1 data cache config, i.e., {<config>|none}",
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&cache_dl1_opt, "dl1:256:32:1:l", /* print */TRUE, NULL);
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opt_reg_note(odb,
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" The cache config parameter <config> has the following format:\n"
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"\n"
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" <name>:<nsets>:<bsize>:<assoc>:<repl>\n"
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"\n"
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" <name> - name of the cache being defined\n"
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" <nsets> - number of sets in the cache\n"
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" <bsize> - block size of the cache\n"
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" <assoc> - associativity of the cache\n"
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" <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random\n"
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"\n"
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" Examples: -cache:dl1 dl1:4096:32:1:l\n"
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" -dtlb dtlb:128:4096:32:r\n"
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);
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opt_reg_string(odb, "-cache:dl2",
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"l2 data cache config, i.e., {<config>|none}",
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&cache_dl2_opt, "ul2:1024:64:4:l", /* print */TRUE, NULL);
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opt_reg_string(odb, "-cache:il1",
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"l1 inst cache config, i.e., {<config>|dl1|dl2|none}",
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&cache_il1_opt, "il1:256:32:1:l", /* print */TRUE, NULL);
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opt_reg_note(odb,
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" Cache levels can be unified by pointing a level of the instruction cache\n"
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" hierarchy at the data cache hiearchy using the \"dl1\" and \"dl2\" cache\n"
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" configuration arguments. Most sensible combinations are supported, e.g.,\n"
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"\n"
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" A unified l2 cache (il2 is pointed at dl2):\n"
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" -cache:il1 il1:128:64:1:l -cache:il2 dl2\n"
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" -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l\n"
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"\n"
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" Or, a fully unified cache hierarchy (il1 pointed at dl1):\n"
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" -cache:il1 dl1\n"
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" -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l\n"
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);
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opt_reg_string(odb, "-cache:il2",
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"l2 instruction cache config, i.e., {<config>|dl2|none}",
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&cache_il2_opt, "dl2", /* print */TRUE, NULL);
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opt_reg_string(odb, "-tlb:itlb",
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"instruction TLB config, i.e., {<config>|none}",
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&itlb_opt, "itlb:16:4096:4:l", /* print */TRUE, NULL);
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opt_reg_string(odb, "-tlb:dtlb",
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"data TLB config, i.e., {<config>|none}",
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&dtlb_opt, "dtlb:32:4096:4:l", /* print */TRUE, NULL);
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opt_reg_flag(odb, "-flush", "flush caches on system calls",
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&flush_on_syscalls, /* default */FALSE, /* print */TRUE, NULL);
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opt_reg_flag(odb, "-cache:icompress",
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"convert 64-bit inst addresses to 32-bit inst equivalents",
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&compress_icache_addrs, /* default */FALSE,
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/* print */TRUE, NULL);
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opt_reg_string_list(odb, "-pcstat",
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"profile stat(s) against text addr's (mult uses ok)",
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pcstat_vars, MAX_PCSTAT_VARS, &pcstat_nelt, NULL,
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/* !print */FALSE, /* format */NULL, /* accrue */TRUE);
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}
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/* check simulator-specific option values */
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void
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sim_check_options(struct opt_odb_t *odb, /* options database */
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int argc, char **argv) /* command line arguments */
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{
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char name[128], c;
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int nsets, bsize, assoc;
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/* use a level 1 D-cache? */
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if (!mystricmp(cache_dl1_opt, "none"))
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{
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cache_dl1 = NULL;
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/* the level 2 D-cache cannot be defined */
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if (strcmp(cache_dl2_opt, "none"))
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fatal("the l1 data cache must defined if the l2 cache is defined");
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cache_dl2 = NULL;
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}
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else /* dl1 is defined */
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{
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if (sscanf(cache_dl1_opt, "%[^:]:%d:%d:%d:%c",
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name, &nsets, &bsize, &assoc, &c) != 5)
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fatal("bad l1 D-cache parms: <name>:<nsets>:<bsize>:<assoc>:<repl>");
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cache_dl1 = cache_create(name, nsets, bsize, /* balloc */FALSE,
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/* usize */0, assoc, cache_char2policy(c),
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dl1_access_fn, /* hit latency */1);
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/* is the level 2 D-cache defined? */
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if (!mystricmp(cache_dl2_opt, "none"))
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cache_dl2 = NULL;
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else
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{
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if (sscanf(cache_dl2_opt, "%[^:]:%d:%d:%d:%c",
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name, &nsets, &bsize, &assoc, &c) != 5)
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fatal("bad l2 D-cache parms: "
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"<name>:<nsets>:<bsize>:<assoc>:<repl>");
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cache_dl2 = cache_create(name, nsets, bsize, /* balloc */FALSE,
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/* usize */0, assoc, cache_char2policy(c),
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dl2_access_fn, /* hit latency */1);
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}
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}
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/* use a level 1 I-cache? */
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if (!mystricmp(cache_il1_opt, "none"))
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{
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cache_il1 = NULL;
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/* the level 2 I-cache cannot be defined */
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if (strcmp(cache_il2_opt, "none"))
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fatal("the l1 inst cache must defined if the l2 cache is defined");
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cache_il2 = NULL;
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}
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else if (!mystricmp(cache_il1_opt, "dl1"))
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{
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if (!cache_dl1)
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fatal("I-cache l1 cannot access D-cache l1 as it's undefined");
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cache_il1 = cache_dl1;
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/* the level 2 I-cache cannot be defined */
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if (strcmp(cache_il2_opt, "none"))
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fatal("the l1 inst cache must defined if the l2 cache is defined");
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cache_il2 = NULL;
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}
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else if (!mystricmp(cache_il1_opt, "dl2"))
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{
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if (!cache_dl2)
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fatal("I-cache l1 cannot access D-cache l2 as it's undefined");
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cache_il1 = cache_dl2;
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/* the level 2 I-cache cannot be defined */
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if (strcmp(cache_il2_opt, "none"))
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fatal("the l1 inst cache must defined if the l2 cache is defined");
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cache_il2 = NULL;
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}
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else /* il1 is defined */
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{
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if (sscanf(cache_il1_opt, "%[^:]:%d:%d:%d:%c",
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name, &nsets, &bsize, &assoc, &c) != 5)
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fatal("bad l1 I-cache parms: <name>:<nsets>:<bsize>:<assoc>:<repl>");
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cache_il1 = cache_create(name, nsets, bsize, /* balloc */FALSE,
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/* usize */0, assoc, cache_char2policy(c),
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il1_access_fn, /* hit latency */1);
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/* is the level 2 D-cache defined? */
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if (!mystricmp(cache_il2_opt, "none"))
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cache_il2 = NULL;
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else if (!mystricmp(cache_il2_opt, "dl2"))
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{
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if (!cache_dl2)
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fatal("I-cache l2 cannot access D-cache l2 as it's undefined");
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cache_il2 = cache_dl2;
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}
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else
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{
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if (sscanf(cache_il2_opt, "%[^:]:%d:%d:%d:%c",
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name, &nsets, &bsize, &assoc, &c) != 5)
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fatal("bad l2 I-cache parms: "
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"<name>:<nsets>:<bsize>:<assoc>:<repl>");
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cache_il2 = cache_create(name, nsets, bsize, /* balloc */FALSE,
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/* usize */0, assoc, cache_char2policy(c),
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il2_access_fn, /* hit latency */1);
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}
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}
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/* use an I-TLB? */
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if (!mystricmp(itlb_opt, "none"))
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itlb = NULL;
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else
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{
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if (sscanf(itlb_opt, "%[^:]:%d:%d:%d:%c",
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name, &nsets, &bsize, &assoc, &c) != 5)
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fatal("bad TLB parms: <name>:<nsets>:<page_size>:<assoc>:<repl>");
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itlb = cache_create(name, nsets, bsize, /* balloc */FALSE,
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/* usize */sizeof(md_addr_t), assoc,
|
|
cache_char2policy(c), itlb_access_fn,
|
|
/* hit latency */1);
|
|
}
|
|
|
|
/* use a D-TLB? */
|
|
if (!mystricmp(dtlb_opt, "none"))
|
|
dtlb = NULL;
|
|
else
|
|
{
|
|
if (sscanf(dtlb_opt, "%[^:]:%d:%d:%d:%c",
|
|
name, &nsets, &bsize, &assoc, &c) != 5)
|
|
fatal("bad TLB parms: <name>:<nsets>:<page_size>:<assoc>:<repl>");
|
|
dtlb = cache_create(name, nsets, bsize, /* balloc */FALSE,
|
|
/* usize */sizeof(md_addr_t), assoc,
|
|
cache_char2policy(c), dtlb_access_fn,
|
|
/* hit latency */1);
|
|
}
|
|
}
|
|
|
|
/* initialize the simulator */
|
|
void
|
|
sim_init(void)
|
|
{
|
|
sim_num_refs = 0;
|
|
|
|
/* allocate and initialize register file */
|
|
regs_init(®s);
|
|
|
|
/* allocate and initialize memory space */
|
|
mem = mem_create("mem");
|
|
mem_init(mem);
|
|
}
|
|
|
|
/* local machine state accessor */
|
|
static char * /* err str, NULL for no err */
|
|
cache_mstate_obj(FILE *stream, /* output stream */
|
|
char *cmd, /* optional command string */
|
|
struct regs_t *regs, /* register to access */
|
|
struct mem_t *mem) /* memory to access */
|
|
{
|
|
/* just dump intermediate stats */
|
|
sim_print_stats(stream);
|
|
|
|
/* no error */
|
|
return NULL;
|
|
}
|
|
|
|
/* load program into simulated state */
|
|
void
|
|
sim_load_prog(char *fname, /* program to load */
|
|
int argc, char **argv, /* program arguments */
|
|
char **envp) /* program environment */
|
|
{
|
|
/* load program text and data, set up environment, memory, and regs */
|
|
ld_load_prog(fname, argc, argv, envp, ®s, mem, TRUE);
|
|
|
|
/* initialize the DLite debugger */
|
|
dlite_init(md_reg_obj, dlite_mem_obj, cache_mstate_obj);
|
|
}
|
|
|
|
/* print simulator-specific configuration information */
|
|
void
|
|
sim_aux_config(FILE *stream) /* output stream */
|
|
{
|
|
/* nada */
|
|
}
|
|
|
|
/* register simulator-specific statistics */
|
|
void
|
|
sim_reg_stats(struct stat_sdb_t *sdb) /* stats database */
|
|
{
|
|
int i;
|
|
|
|
/* register baseline stats */
|
|
stat_reg_counter(sdb, "sim_num_insn",
|
|
"total number of instructions executed",
|
|
&sim_num_insn, sim_num_insn, NULL);
|
|
stat_reg_counter(sdb, "sim_num_refs",
|
|
"total number of loads and stores executed",
|
|
&sim_num_refs, 0, NULL);
|
|
stat_reg_int(sdb, "sim_elapsed_time",
|
|
"total simulation time in seconds",
|
|
&sim_elapsed_time, 0, NULL);
|
|
stat_reg_formula(sdb, "sim_inst_rate",
|
|
"simulation speed (in insts/sec)",
|
|
"sim_num_insn / sim_elapsed_time", NULL);
|
|
|
|
/* register cache stats */
|
|
if (cache_il1
|
|
&& (cache_il1 != cache_dl1 && cache_il1 != cache_dl2))
|
|
cache_reg_stats(cache_il1, sdb);
|
|
if (cache_il2
|
|
&& (cache_il2 != cache_dl1 && cache_il2 != cache_dl2))
|
|
cache_reg_stats(cache_il2, sdb);
|
|
if (cache_dl1)
|
|
cache_reg_stats(cache_dl1, sdb);
|
|
if (cache_dl2)
|
|
cache_reg_stats(cache_dl2, sdb);
|
|
if (itlb)
|
|
cache_reg_stats(itlb, sdb);
|
|
if (dtlb)
|
|
cache_reg_stats(dtlb, sdb);
|
|
|
|
for (i=0; i<pcstat_nelt; i++)
|
|
{
|
|
char buf[512], buf1[512];
|
|
struct stat_stat_t *stat;
|
|
|
|
/* track the named statistical variable by text address */
|
|
|
|
/* find it... */
|
|
stat = stat_find_stat(sdb, pcstat_vars[i]);
|
|
if (!stat)
|
|
fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
|
|
|
|
/* stat must be an integral type */
|
|
if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
|
|
fatal("`-pcstat' statistical variable `%s' is not an integral type",
|
|
stat->name);
|
|
|
|
/* register this stat */
|
|
pcstat_stats[i] = stat;
|
|
pcstat_lastvals[i] = STATVAL(stat);
|
|
|
|
/* declare the sparce text distribution */
|
|
sprintf(buf, "%s_by_pc", stat->name);
|
|
sprintf(buf1, "%s (by text address)", stat->desc);
|
|
pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
|
|
/* initial value */0,
|
|
/* print fmt */(PF_COUNT|PF_PDF),
|
|
/* format */"0x%p %u %.2f",
|
|
/* print fn */NULL);
|
|
}
|
|
ld_reg_stats(sdb);
|
|
mem_reg_stats(mem, sdb);
|
|
}
|
|
|
|
/* dump simulator-specific auxiliary simulator statistics */
|
|
void
|
|
sim_aux_stats(FILE *stream) /* output stream */
|
|
{
|
|
/* nada */
|
|
}
|
|
|
|
/* un-initialize the simulator */
|
|
void
|
|
sim_uninit(void)
|
|
{
|
|
/* nada */
|
|
}
|
|
|
|
/*
|
|
* configure the execution engine
|
|
*/
|
|
|
|
/*
|
|
* precise architected register accessors
|
|
*/
|
|
|
|
/* next program counter */
|
|
#define SET_NPC(EXPR) (regs.regs_NPC = (EXPR))
|
|
|
|
/* current program counter */
|
|
#define CPC (regs.regs_PC)
|
|
|
|
/* general purpose registers */
|
|
#define GPR(N) (regs.regs_R[N])
|
|
#define SET_GPR(N,EXPR) (regs.regs_R[N] = (EXPR))
|
|
|
|
#if defined(TARGET_PISA)
|
|
|
|
/* floating point registers, L->word, F->single-prec, D->double-prec */
|
|
#define FPR_L(N) (regs.regs_F.l[(N)])
|
|
#define SET_FPR_L(N,EXPR) (regs.regs_F.l[(N)] = (EXPR))
|
|
#define FPR_F(N) (regs.regs_F.f[(N)])
|
|
#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))
|
|
#define FPR_D(N) (regs.regs_F.d[(N) >> 1])
|
|
#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = (EXPR))
|
|
|
|
/* miscellaneous register accessors */
|
|
#define SET_HI(EXPR) (regs.regs_C.hi = (EXPR))
|
|
#define HI (regs.regs_C.hi)
|
|
#define SET_LO(EXPR) (regs.regs_C.lo = (EXPR))
|
|
#define LO (regs.regs_C.lo)
|
|
#define FCC (regs.regs_C.fcc)
|
|
#define SET_FCC(EXPR) (regs.regs_C.fcc = (EXPR))
|
|
|
|
#elif defined(TARGET_ALPHA)
|
|
|
|
/* floating point registers, L->word, F->single-prec, D->double-prec */
|
|
#define FPR_Q(N) (regs.regs_F.q[N])
|
|
#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[N] = (EXPR))
|
|
#define FPR(N) (regs.regs_F.d[N])
|
|
#define SET_FPR(N,EXPR) (regs.regs_F.d[N] = (EXPR))
|
|
|
|
/* miscellaneous register accessors */
|
|
#define FPCR (regs.regs_C.fpcr)
|
|
#define SET_FPCR(EXPR) (regs.regs_C.fpcr = (EXPR))
|
|
#define UNIQ (regs.regs_C.uniq)
|
|
#define SET_UNIQ(EXPR) (regs.regs_C.uniq = (EXPR))
|
|
|
|
#else
|
|
#error No ISA target defined...
|
|
#endif
|
|
|
|
/* precise architected memory state accessor macros */
|
|
#define __READ_CACHE(addr, SRC_T) \
|
|
((dtlb \
|
|
? cache_access(dtlb, Read, (addr), NULL, \
|
|
sizeof(SRC_T), 0, NULL, NULL) \
|
|
: 0), \
|
|
(cache_dl1 \
|
|
? cache_access(cache_dl1, Read, (addr), NULL, \
|
|
sizeof(SRC_T), 0, NULL, NULL) \
|
|
: 0))
|
|
|
|
#define READ_BYTE(SRC, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (SRC), \
|
|
__READ_CACHE(addr, byte_t), MEM_READ_BYTE(mem, addr))
|
|
#define READ_HALF(SRC, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (SRC), \
|
|
__READ_CACHE(addr, half_t), MEM_READ_HALF(mem, addr))
|
|
#define READ_WORD(SRC, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (SRC), \
|
|
__READ_CACHE(addr, word_t), MEM_READ_WORD(mem, addr))
|
|
#ifdef HOST_HAS_QWORD
|
|
#define READ_QWORD(SRC, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (SRC), \
|
|
__READ_CACHE(addr, qword_t), MEM_READ_QWORD(mem, addr))
|
|
#endif /* HOST_HAS_QWORD */
|
|
|
|
#define __WRITE_CACHE(addr, DST_T) \
|
|
((dtlb \
|
|
? cache_access(dtlb, Write, (addr), NULL, \
|
|
sizeof(DST_T), 0, NULL, NULL) \
|
|
: 0), \
|
|
(cache_dl1 \
|
|
? cache_access(cache_dl1, Write, (addr), NULL, \
|
|
sizeof(DST_T), 0, NULL, NULL) \
|
|
: 0))
|
|
|
|
#define WRITE_BYTE(SRC, DST, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (DST), \
|
|
__WRITE_CACHE(addr, byte_t), MEM_WRITE_BYTE(mem, addr, (SRC)))
|
|
#define WRITE_HALF(SRC, DST, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (DST), \
|
|
__WRITE_CACHE(addr, half_t), MEM_WRITE_HALF(mem, addr, (SRC)))
|
|
#define WRITE_WORD(SRC, DST, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (DST), \
|
|
__WRITE_CACHE(addr, word_t), MEM_WRITE_WORD(mem, addr, (SRC)))
|
|
#ifdef HOST_HAS_QWORD
|
|
#define WRITE_QWORD(SRC, DST, FAULT) \
|
|
((FAULT) = md_fault_none, addr = (DST), \
|
|
__WRITE_CACHE(addr, qword_t), MEM_WRITE_QWORD(mem, addr, (SRC)))
|
|
#endif /* HOST_HAS_QWORD */
|
|
|
|
/* system call memory access function */
|
|
enum md_fault_type
|
|
dcache_access_fn(struct mem_t *mem, /* memory space to access */
|
|
enum mem_cmd cmd, /* memory access cmd, Read or Write */
|
|
md_addr_t addr, /* data address to access */
|
|
void *p, /* data input/output buffer */
|
|
int nbytes) /* number of bytes to access */
|
|
{
|
|
if (dtlb)
|
|
cache_access(dtlb, cmd, addr, NULL, nbytes, 0, NULL, NULL);
|
|
if (cache_dl1)
|
|
cache_access(cache_dl1, cmd, addr, NULL, nbytes, 0, NULL, NULL);
|
|
return mem_access(mem, cmd, addr, p, nbytes);
|
|
}
|
|
|
|
/* system call handler macro */
|
|
#define SYSCALL(INST) \
|
|
(flush_on_syscalls \
|
|
? ((dtlb ? cache_flush(dtlb, 0) : 0), \
|
|
(cache_dl1 ? cache_flush(cache_dl1, 0) : 0), \
|
|
(cache_dl2 ? cache_flush(cache_dl2, 0) : 0), \
|
|
sys_syscall(®s, mem_access, mem, INST, TRUE)) \
|
|
: sys_syscall(®s, dcache_access_fn, mem, INST, TRUE))
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
void
|
|
sim_main(void)
|
|
{
|
|
int i;
|
|
md_inst_t inst;
|
|
register md_addr_t addr;
|
|
enum md_opcode op;
|
|
register int is_write;
|
|
enum md_fault_type fault;
|
|
|
|
fprintf(stderr, "sim: ** starting functional simulation w/ caches **\n");
|
|
|
|
/* set up initial default next PC */
|
|
regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
|
|
|
|
/* check for DLite debugger entry condition */
|
|
if (dlite_check_break(regs.regs_PC, /* no access */0, /* addr */0, 0, 0))
|
|
dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
|
|
sim_num_insn, ®s, mem);
|
|
|
|
while (TRUE)
|
|
{
|
|
/* maintain $r0 semantics */
|
|
regs.regs_R[MD_REG_ZERO] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
regs.regs_F.d[MD_REG_ZERO] = 0.0;
|
|
#endif /* TARGET_ALPHA */
|
|
|
|
/* get the next instruction to execute */
|
|
if (itlb)
|
|
cache_access(itlb, Read, IACOMPRESS(regs.regs_PC),
|
|
NULL, ISCOMPRESS(sizeof(md_inst_t)), 0, NULL, NULL);
|
|
if (cache_il1)
|
|
cache_access(cache_il1, Read, IACOMPRESS(regs.regs_PC),
|
|
NULL, ISCOMPRESS(sizeof(md_inst_t)), 0, NULL, NULL);
|
|
MD_FETCH_INST(inst, mem, regs.regs_PC);
|
|
|
|
/* keep an instruction count */
|
|
sim_num_insn++;
|
|
|
|
/* set default reference address and access mode */
|
|
addr = 0; is_write = FALSE;
|
|
|
|
/* set default fault - none */
|
|
fault = md_fault_none;
|
|
|
|
/* decode the instruction */
|
|
MD_SET_OPCODE(op, inst);
|
|
|
|
/* execute the instruction */
|
|
switch (op)
|
|
{
|
|
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
|
|
case OP: \
|
|
SYMCAT(OP,_IMPL); \
|
|
break;
|
|
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
|
|
case OP: \
|
|
panic("attempted to execute a linking opcode");
|
|
#define CONNECT(OP)
|
|
#define DECLARE_FAULT(FAULT) \
|
|
{ fault = (FAULT); break; }
|
|
#include "machine.def"
|
|
default:
|
|
panic("attempted to execute a bogus opcode");
|
|
}
|
|
|
|
if (fault != md_fault_none)
|
|
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
|
|
|
|
if (MD_OP_FLAGS(op) & F_MEM)
|
|
{
|
|
sim_num_refs++;
|
|
if (MD_OP_FLAGS(op) & F_STORE)
|
|
is_write = TRUE;
|
|
}
|
|
|
|
/* update any stats tracked by PC */
|
|
for (i=0; i < pcstat_nelt; i++)
|
|
{
|
|
counter_t newval;
|
|
int delta;
|
|
|
|
/* check if any tracked stats changed */
|
|
newval = STATVAL(pcstat_stats[i]);
|
|
delta = newval - pcstat_lastvals[i];
|
|
if (delta != 0)
|
|
{
|
|
stat_add_samples(pcstat_sdists[i], regs.regs_PC, delta);
|
|
pcstat_lastvals[i] = newval;
|
|
}
|
|
|
|
}
|
|
|
|
/* check for DLite debugger entry condition */
|
|
if (dlite_check_break(regs.regs_NPC,
|
|
is_write ? ACCESS_WRITE : ACCESS_READ,
|
|
addr, sim_num_insn, sim_num_insn))
|
|
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
|
|
|
|
/* go to the next instruction */
|
|
regs.regs_PC = regs.regs_NPC;
|
|
regs.regs_NPC += sizeof(md_inst_t);
|
|
|
|
/* finish early? */
|
|
if (max_insts && sim_num_insn >= max_insts)
|
|
return;
|
|
}
|
|
}
|