565 lines
18 KiB
C
565 lines
18 KiB
C
/* sim-bpred.c - sample branch predictor simulator implementation */
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/* SimpleScalar(TM) Tool Suite
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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* All Rights Reserved.
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*
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* THIS IS A LEGAL DOCUMENT, BY USING SIMPLESCALAR,
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* YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
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*
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* No portion of this work may be used by any commercial entity, or for any
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* commercial purpose, without the prior, written permission of SimpleScalar,
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* LLC (info@simplescalar.com). Nonprofit and noncommercial use is permitted
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* as described below.
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*
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* 1. SimpleScalar is provided AS IS, with no warranty of any kind, express
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* or implied. The user of the program accepts full responsibility for the
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* application of the program and the use of any results.
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*
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* 2. Nonprofit and noncommercial use is encouraged. SimpleScalar may be
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* downloaded, compiled, executed, copied, and modified solely for nonprofit,
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* educational, noncommercial research, and noncommercial scholarship
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* purposes provided that this notice in its entirety accompanies all copies.
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* Copies of the modified software can be delivered to persons who use it
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* solely for nonprofit, educational, noncommercial research, and
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* noncommercial scholarship purposes provided that this notice in its
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* entirety accompanies all copies.
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*
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* 3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT ENTITIES, IS EXPRESSLY
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* PROHIBITED WITHOUT A LICENSE FROM SIMPLESCALAR, LLC (info@simplescalar.com).
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*
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* 4. No nonprofit user may place any restrictions on the use of this software,
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* including as modified by the user, by any other authorized user.
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*
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* 5. Noncommercial and nonprofit users may distribute copies of SimpleScalar
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* in compiled or executable form as set forth in Section 2, provided that
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* either: (A) it is accompanied by the corresponding machine-readable source
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* code, or (B) it is accompanied by a written offer, with no time limit, to
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* give anyone a machine-readable copy of the corresponding source code in
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* return for reimbursement of the cost of distribution. This written offer
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* must permit verbatim duplication by anyone, or (C) it is distributed by
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* someone who received only the executable form, and is accompanied by a
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* copy of the written offer of source code.
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*
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* 6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool suite is
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* currently maintained by SimpleScalar LLC (info@simplescalar.com). US Mail:
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* 2395 Timbercrest Court, Ann Arbor, MI 48105.
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*
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* Copyright (C) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include "host.h"
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#include "misc.h"
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#include "machine.h"
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#include "regs.h"
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#include "memory.h"
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#include "loader.h"
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#include "syscall.h"
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#include "dlite.h"
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#include "options.h"
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#include "stats.h"
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#include "bpred.h"
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#include "sim.h"
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/*
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* This file implements a branch predictor analyzer.
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*/
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/* simulated registers */
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static struct regs_t regs;
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/* simulated memory */
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static struct mem_t *mem = NULL;
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/* maximum number of inst's to execute */
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static unsigned int max_insts;
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/* branch predictor type {nottaken|taken|perfect|bimod|2lev} */
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static char *pred_type;
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/* bimodal predictor config (<table_size>) */
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static int bimod_nelt = 1;
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static int bimod_config[1] =
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{ /* bimod tbl size */2048 };
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/* 2-level predictor config (<l1size> <l2size> <hist_size> <xor>) */
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static int twolev_nelt = 4;
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static int twolev_config[4] =
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{ /* l1size */1, /* l2size */1024, /* hist */8, /* xor */FALSE};
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/* combining predictor config (<meta_table_size> */
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static int comb_nelt = 1;
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static int comb_config[1] =
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{ /* meta_table_size */1024 };
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/* return address stack (RAS) size */
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static int ras_size = 8;
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/* BTB predictor config (<num_sets> <associativity>) */
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static int btb_nelt = 2;
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static int btb_config[2] =
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{ /* nsets */512, /* assoc */4 };
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/* branch predictor */
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static struct bpred_t *pred;
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/* track number of insn and refs */
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static counter_t sim_num_refs = 0;
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/* total number of branches executed */
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static counter_t sim_num_branches = 0;
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/* register simulator-specific options */
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void
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sim_reg_options(struct opt_odb_t *odb)
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{
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opt_reg_header(odb,
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"sim-bpred: This simulator implements a branch predictor analyzer.\n"
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);
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/* branch predictor options */
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opt_reg_note(odb,
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" Branch predictor configuration examples for 2-level predictor:\n"
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" Configurations: N, M, W, X\n"
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" N # entries in first level (# of shift register(s))\n"
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" W width of shift register(s)\n"
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" M # entries in 2nd level (# of counters, or other FSM)\n"
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" X (yes-1/no-0) xor history and address for 2nd level index\n"
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" Sample predictors:\n"
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" GAg : 1, W, 2^W, 0\n"
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" GAp : 1, W, M (M > 2^W), 0\n"
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" PAg : N, W, 2^W, 0\n"
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" PAp : N, W, M (M == 2^(N+W)), 0\n"
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" gshare : 1, W, 2^W, 1\n"
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" Predictor `comb' combines a bimodal and a 2-level predictor.\n"
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);
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/* instruction limit */
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opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
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&max_insts, /* default */0,
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/* print */TRUE, /* format */NULL);
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opt_reg_string(odb, "-bpred",
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"branch predictor type {nottaken|taken|bimod|2lev|comb}",
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&pred_type, /* default */"bimod",
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/* print */TRUE, /* format */NULL);
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opt_reg_int_list(odb, "-bpred:bimod",
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"bimodal predictor config (<table size>)",
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bimod_config, bimod_nelt, &bimod_nelt,
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/* default */bimod_config,
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/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
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opt_reg_int_list(odb, "-bpred:2lev",
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"2-level predictor config "
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"(<l1size> <l2size> <hist_size> <xor>)",
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twolev_config, twolev_nelt, &twolev_nelt,
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/* default */twolev_config,
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/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
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opt_reg_int_list(odb, "-bpred:comb",
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"combining predictor config (<meta_table_size>)",
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comb_config, comb_nelt, &comb_nelt,
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/* default */comb_config,
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/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
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opt_reg_int(odb, "-bpred:ras",
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"return address stack size (0 for no return stack)",
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&ras_size, /* default */ras_size,
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/* print */TRUE, /* format */NULL);
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opt_reg_int_list(odb, "-bpred:btb",
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"BTB config (<num_sets> <associativity>)",
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btb_config, btb_nelt, &btb_nelt,
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/* default */btb_config,
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/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
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}
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/* check simulator-specific option values */
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void
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sim_check_options(struct opt_odb_t *odb, int argc, char **argv)
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{
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if (!mystricmp(pred_type, "taken"))
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{
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/* static predictor, not taken */
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pred = bpred_create(BPredTaken, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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}
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else if (!mystricmp(pred_type, "nottaken"))
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{
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/* static predictor, taken */
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pred = bpred_create(BPredNotTaken, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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}
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else if (!mystricmp(pred_type, "bimod"))
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{
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if (bimod_nelt != 1)
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fatal("bad bimod predictor config (<table_size>)");
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if (btb_nelt != 2)
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fatal("bad btb config (<num_sets> <associativity>)");
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/* bimodal predictor, bpred_create() checks BTB_SIZE */
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pred = bpred_create(BPred2bit,
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/* bimod table size */bimod_config[0],
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/* 2lev l1 size */0,
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/* 2lev l2 size */0,
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/* meta table size */0,
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/* history reg size */0,
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/* history xor address */0,
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/* btb sets */btb_config[0],
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/* btb assoc */btb_config[1],
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/* ret-addr stack size */ras_size);
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}
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else if (!mystricmp(pred_type, "2lev"))
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{
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/* 2-level adaptive predictor, bpred_create() checks args */
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if (twolev_nelt != 4)
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fatal("bad 2-level pred config (<l1size> <l2size> <hist_size> <xor>)");
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if (btb_nelt != 2)
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fatal("bad btb config (<num_sets> <associativity>)");
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pred = bpred_create(BPred2Level,
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/* bimod table size */0,
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/* 2lev l1 size */twolev_config[0],
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/* 2lev l2 size */twolev_config[1],
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/* meta table size */0,
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/* history reg size */twolev_config[2],
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/* history xor address */twolev_config[3],
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/* btb sets */btb_config[0],
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/* btb assoc */btb_config[1],
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/* ret-addr stack size */ras_size);
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}
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else if (!mystricmp(pred_type, "comb"))
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{
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/* combining predictor, bpred_create() checks args */
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if (twolev_nelt != 4)
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fatal("bad 2-level pred config (<l1size> <l2size> <hist_size> <xor>)");
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if (bimod_nelt != 1)
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fatal("bad bimod predictor config (<table_size>)");
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if (comb_nelt != 1)
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fatal("bad combining predictor config (<meta_table_size>)");
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if (btb_nelt != 2)
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fatal("bad btb config (<num_sets> <associativity>)");
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pred = bpred_create(BPredComb,
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/* bimod table size */bimod_config[0],
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/* l1 size */twolev_config[0],
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/* l2 size */twolev_config[1],
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/* meta table size */comb_config[0],
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/* history reg size */twolev_config[2],
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/* history xor address */twolev_config[3],
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/* btb sets */btb_config[0],
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/* btb assoc */btb_config[1],
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/* ret-addr stack size */ras_size);
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}
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else
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fatal("cannot parse predictor type `%s'", pred_type);
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}
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/* register simulator-specific statistics */
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void
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sim_reg_stats(struct stat_sdb_t *sdb)
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{
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stat_reg_counter(sdb, "sim_num_insn",
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"total number of instructions executed",
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&sim_num_insn, sim_num_insn, NULL);
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stat_reg_counter(sdb, "sim_num_refs",
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"total number of loads and stores executed",
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&sim_num_refs, 0, NULL);
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stat_reg_int(sdb, "sim_elapsed_time",
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"total simulation time in seconds",
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&sim_elapsed_time, 0, NULL);
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stat_reg_formula(sdb, "sim_inst_rate",
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"simulation speed (in insts/sec)",
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"sim_num_insn / sim_elapsed_time", NULL);
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stat_reg_counter(sdb, "sim_num_branches",
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"total number of branches executed",
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&sim_num_branches, /* initial value */0, /* format */NULL);
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stat_reg_formula(sdb, "sim_IPB",
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"instruction per branch",
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"sim_num_insn / sim_num_branches", /* format */NULL);
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/* register predictor stats */
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if (pred)
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bpred_reg_stats(pred, sdb);
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}
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/* initialize the simulator */
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void
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sim_init(void)
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{
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sim_num_refs = 0;
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/* allocate and initialize register file */
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regs_init(®s);
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/* allocate and initialize memory space */
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mem = mem_create("mem");
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mem_init(mem);
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}
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/* local machine state accessor */
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static char * /* err str, NULL for no err */
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bpred_mstate_obj(FILE *stream, /* output stream */
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char *cmd, /* optional command string */
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struct regs_t *regs, /* register to access */
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struct mem_t *mem) /* memory to access */
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{
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/* just dump intermediate stats */
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sim_print_stats(stream);
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/* no error */
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return NULL;
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}
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/* load program into simulated state */
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void
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sim_load_prog(char *fname, /* program to load */
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int argc, char **argv, /* program arguments */
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char **envp) /* program environment */
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{
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/* load program text and data, set up environment, memory, and regs */
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ld_load_prog(fname, argc, argv, envp, ®s, mem, TRUE);
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/* initialize the DLite debugger */
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dlite_init(md_reg_obj, dlite_mem_obj, bpred_mstate_obj);
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}
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/* print simulator-specific configuration information */
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void
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sim_aux_config(FILE *stream) /* output stream */
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{
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/* nothing currently */
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}
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/* dump simulator-specific auxiliary simulator statistics */
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void
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sim_aux_stats(FILE *stream) /* output stream */
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{
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/* nada */
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}
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/* un-initialize simulator-specific state */
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void
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sim_uninit(void)
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{
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/* nada */
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}
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/*
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* configure the execution engine
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*/
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/*
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* precise architected register accessors
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*/
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/* next program counter */
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#define SET_NPC(EXPR) (regs.regs_NPC = (EXPR))
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/* target program counter */
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#undef SET_TPC
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#define SET_TPC(EXPR) (target_PC = (EXPR))
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/* current program counter */
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#define CPC (regs.regs_PC)
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/* general purpose registers */
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#define GPR(N) (regs.regs_R[N])
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#define SET_GPR(N,EXPR) (regs.regs_R[N] = (EXPR))
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#if defined(TARGET_PISA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_L(N) (regs.regs_F.l[(N)])
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#define SET_FPR_L(N,EXPR) (regs.regs_F.l[(N)] = (EXPR))
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#define FPR_F(N) (regs.regs_F.f[(N)])
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#define SET_FPR_F(N,EXPR) (regs.regs_F.f[(N)] = (EXPR))
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#define FPR_D(N) (regs.regs_F.d[(N) >> 1])
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#define SET_FPR_D(N,EXPR) (regs.regs_F.d[(N) >> 1] = (EXPR))
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/* miscellaneous register accessors */
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#define SET_HI(EXPR) (regs.regs_C.hi = (EXPR))
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#define HI (regs.regs_C.hi)
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#define SET_LO(EXPR) (regs.regs_C.lo = (EXPR))
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#define LO (regs.regs_C.lo)
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#define FCC (regs.regs_C.fcc)
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#define SET_FCC(EXPR) (regs.regs_C.fcc = (EXPR))
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#elif defined(TARGET_ALPHA)
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/* floating point registers, L->word, F->single-prec, D->double-prec */
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#define FPR_Q(N) (regs.regs_F.q[N])
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#define SET_FPR_Q(N,EXPR) (regs.regs_F.q[N] = (EXPR))
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#define FPR(N) (regs.regs_F.d[N])
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#define SET_FPR(N,EXPR) (regs.regs_F.d[N] = (EXPR))
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/* miscellaneous register accessors */
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#define FPCR (regs.regs_C.fpcr)
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#define SET_FPCR(EXPR) (regs.regs_C.fpcr = (EXPR))
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#define UNIQ (regs.regs_C.uniq)
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#define SET_UNIQ(EXPR) (regs.regs_C.uniq = (EXPR))
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#else
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#error No ISA target defined...
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#endif
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/* precise architected memory state help functions */
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#define READ_BYTE(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_BYTE(mem, addr))
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#define READ_HALF(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_HALF(mem, addr))
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#define READ_WORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_WORD(mem, addr))
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#ifdef HOST_HAS_QWORD
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#define READ_QWORD(SRC, FAULT) \
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((FAULT) = md_fault_none, addr = (SRC), MEM_READ_QWORD(mem, addr))
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#endif /* HOST_HAS_QWORD */
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#define WRITE_BYTE(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_BYTE(mem, addr, (SRC)))
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#define WRITE_HALF(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_HALF(mem, addr, (SRC)))
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#define WRITE_WORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_WORD(mem, addr, (SRC)))
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#ifdef HOST_HAS_QWORD
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#define WRITE_QWORD(SRC, DST, FAULT) \
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((FAULT) = md_fault_none, addr = (DST), MEM_WRITE_QWORD(mem, addr, (SRC)))
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#endif /* HOST_HAS_QWORD */
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/* system call handler macro */
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#define SYSCALL(INST) sys_syscall(®s, mem_access, mem, INST, TRUE)
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/* start simulation, program loaded, processor precise state initialized */
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void
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sim_main(void)
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{
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md_inst_t inst;
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register md_addr_t addr, target_PC = 0;
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enum md_opcode op;
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register int is_write;
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int stack_idx;
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enum md_fault_type fault;
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fprintf(stderr, "sim: ** starting functional simulation w/ predictors **\n");
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/* set up initial default next PC */
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regs.regs_NPC = regs.regs_PC + sizeof(md_inst_t);
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/* check for DLite debugger entry condition */
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if (dlite_check_break(regs.regs_PC, /* no access */0, /* addr */0, 0, 0))
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dlite_main(regs.regs_PC - sizeof(md_inst_t), regs.regs_PC,
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sim_num_insn, ®s, mem);
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while (TRUE)
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{
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/* maintain $r0 semantics */
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regs.regs_R[MD_REG_ZERO] = 0;
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#ifdef TARGET_ALPHA
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regs.regs_F.d[MD_REG_ZERO] = 0.0;
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#endif /* TARGET_ALPHA */
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/* get the next instruction to execute */
|
|
MD_FETCH_INST(inst, mem, regs.regs_PC);
|
|
|
|
/* keep an instruction count */
|
|
sim_num_insn++;
|
|
|
|
/* set default reference address and access mode */
|
|
addr = 0; is_write = FALSE;
|
|
|
|
/* set default fault - none */
|
|
fault = md_fault_none;
|
|
|
|
/* decode the instruction */
|
|
MD_SET_OPCODE(op, inst);
|
|
|
|
/* execute the instruction */
|
|
switch (op)
|
|
{
|
|
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
|
|
case OP: \
|
|
SYMCAT(OP,_IMPL); \
|
|
break;
|
|
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
|
|
case OP: \
|
|
panic("attempted to execute a linking opcode");
|
|
#define CONNECT(OP)
|
|
#define DECLARE_FAULT(FAULT) \
|
|
{ fault = (FAULT); break; }
|
|
#include "machine.def"
|
|
default:
|
|
panic("attempted to execute a bogus opcode");
|
|
}
|
|
|
|
if (fault != md_fault_none)
|
|
fatal("fault (%d) detected @ 0x%08p", fault, regs.regs_PC);
|
|
|
|
if (MD_OP_FLAGS(op) & F_MEM)
|
|
{
|
|
sim_num_refs++;
|
|
if (MD_OP_FLAGS(op) & F_STORE)
|
|
is_write = TRUE;
|
|
}
|
|
|
|
if (MD_OP_FLAGS(op) & F_CTRL)
|
|
{
|
|
md_addr_t pred_PC;
|
|
struct bpred_update_t update_rec;
|
|
|
|
sim_num_branches++;
|
|
|
|
if (pred)
|
|
{
|
|
/* get the next predicted fetch address */
|
|
pred_PC = bpred_lookup(pred,
|
|
/* branch addr */regs.regs_PC,
|
|
/* target */target_PC,
|
|
/* inst opcode */op,
|
|
/* call? */MD_IS_CALL(op),
|
|
/* return? */MD_IS_RETURN(op),
|
|
/* stash an update ptr */&update_rec,
|
|
/* stash return stack ptr */&stack_idx);
|
|
|
|
/* valid address returned from branch predictor? */
|
|
if (!pred_PC)
|
|
{
|
|
/* no predicted taken target, attempt not taken target */
|
|
pred_PC = regs.regs_PC + sizeof(md_inst_t);
|
|
}
|
|
|
|
bpred_update(pred,
|
|
/* branch addr */regs.regs_PC,
|
|
/* resolved branch target */regs.regs_NPC,
|
|
/* taken? */regs.regs_NPC != (regs.regs_PC +
|
|
sizeof(md_inst_t)),
|
|
/* pred taken? */pred_PC != (regs.regs_PC +
|
|
sizeof(md_inst_t)),
|
|
/* correct pred? */pred_PC == regs.regs_NPC,
|
|
/* opcode */op,
|
|
/* predictor update pointer */&update_rec);
|
|
}
|
|
}
|
|
|
|
/* check for DLite debugger entry condition */
|
|
if (dlite_check_break(regs.regs_NPC,
|
|
is_write ? ACCESS_WRITE : ACCESS_READ,
|
|
addr, sim_num_insn, sim_num_insn))
|
|
dlite_main(regs.regs_PC, regs.regs_NPC, sim_num_insn, ®s, mem);
|
|
|
|
/* go to the next instruction */
|
|
regs.regs_PC = regs.regs_NPC;
|
|
regs.regs_NPC += sizeof(md_inst_t);
|
|
|
|
/* finish early? */
|
|
if (max_insts && sim_num_insn >= max_insts)
|
|
return;
|
|
}
|
|
}
|