Andrew Waterman 4c23c6e9c4 Add ClockGate black box and sample implementation		2018-09-21 22:58:21 -07:00
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.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	Use vlsi_mem_gen for verilator flow	2017-08-07 20:36:22 -07:00
Makefrag	Add ClockGate black box and sample implementation	2018-09-21 22:58:21 -07:00
Makefrag-verilog	Add HasBlackBoxResource to some black boxes.	2018-03-21 17:22:53 -07:00