e007c813c7
TLToAHB: add direct support for Hints
...
As AHB does not support PutPartial and often connects to devices
which have side effects on Gets, the HintHandler cannot provide
Hint support for AHB slaves. Therefore, support Hints directly.
2018-10-03 22:49:00 -07:00
ca22c209cb
HintHandler: add support for Get translation as well
2018-10-03 21:11:14 -07:00
79b392377d
HintHandler: rewrite for simpler hardware
2018-10-03 21:11:09 -07:00
d898b3662e
tilelink: enhance trivial arbiters to reduce to nothing
2018-10-03 21:11:02 -07:00
d3bc1341aa
Merge pull request #1648 from freechipsproject/clock-gating
...
More Rocket clock gating
2018-10-03 19:49:13 -07:00
afd93df40e
Fix CLINT MSIP register addressing
...
This finishes the work started in 1d95fcc882
2018-10-03 17:25:51 -07:00
696955394a
Fix an I$ clock-gating bug
2018-10-03 12:52:02 -07:00
0569672039
Add SCIE to HasCoreParameters
2018-10-03 12:52:02 -07:00
dbe65d79e7
clock-gate the pipeline during D$ misses
2018-10-03 12:52:02 -07:00
c30c89b798
Use Vec instead of Seq for better naming
2018-10-03 12:52:02 -07:00
3b8674dde7
Clock the cycle counter while opportunistically clock gated
...
...but not during WFI.
2018-10-03 12:52:02 -07:00
123cb0ae15
clock gate the fetch unit
2018-10-03 12:52:02 -07:00
180e19223f
Clock gate FPU when no FP instructions are in the pipeline
2018-10-03 12:52:02 -07:00
5186119e5b
Clock gate Rocket core during WFI and I$ misses
2018-10-03 12:52:02 -07:00
00ba2ff8ad
Make the boot ROM mask interrupts before WFIing
2018-10-03 12:52:02 -07:00
9a30c4ba06
Revert "Merge pull request #1650 from freechipsproject/error-devices"
...
This reverts commit 8d4aa8287db688dc7164
2018-10-03 12:51:14 -07:00
ff722d83b0
Revert "Merge pull request #1654 from freechipsproject/better-hints"
...
This reverts commit c9f5f417b91d95fcc882
2018-10-03 12:50:57 -07:00
c9f5f417b9
Merge pull request #1654 from freechipsproject/better-hints
...
Better HintHandler
2018-10-03 11:07:15 -07:00
72d55465ac
HintHandler: add support for Get translation as well
2018-10-02 22:46:24 -07:00
cde972dbc3
HintHandler: rewrite for simpler hardware
2018-10-02 17:24:38 -07:00
19439d6f96
tilelink: enhance trivial arbiters to reduce to nothing
2018-10-02 12:52:27 -07:00
1d95fcc882
changed ipiWidth to 1 to make both CLIC_address and CLINT_address for MSIP byte-addressable ( #1651 )
2018-10-02 11:26:23 -07:00
8d4aa8287d
Merge pull request #1650 from freechipsproject/error-devices
...
Refactor DevNullDevices and provide some within TLBusWrappers
2018-09-30 21:30:43 -07:00
001572ca74
tilelink: more detailed fragmenter requirements
2018-09-30 01:19:55 -07:00
1121226259
diplomacyL LazyScope toString
2018-09-30 01:17:53 -07:00
4d6d00022a
tilelink: refactor error devices
2018-09-30 01:17:23 -07:00
b688dc7164
Merge pull request #1649 from freechipsproject/scie
...
Add Simple Custom Instruction Extension
2018-09-30 01:07:35 -07:00
fcfedefc09
Add Simple Custom Instruction Extension
...
This enables adding custom instructions that operate on the x-registers
(i.e., no additional architectural state).
This version on supports combinational units (which fit in the pipeline in
the same place as the integer ALU), but it can be extended to support 2-stage
pipelines, or multi-cycle operations.
2018-09-29 16:02:36 -07:00
8b27d1832d
tlzero: responds to atomics with 0
2018-09-27 13:36:39 -07:00
ef62d93743
registerrouter: require pow2 size ( #1646 )
2018-09-27 08:55:57 -07:00
d587ae4f4c
Adding no exclude fire() to DecoupledHelper ( #1645 )
...
Adding a no-argument fire() to DecoupledHelper that doesn't exclude anything. The previous way of doing this, which was fire(false.B), was broken by the previous change of requiring all excluded to be included, and forced a further hack of adding a dummy value. Since excluding false.B was a hack in itself, this avoids the issue entirely by providing a straightforward and safe way of excluding nothing.
2018-09-26 16:04:26 -07:00
50bb13d788
Merge pull request #1643 from freechipsproject/update-run-recipes
...
Improve generated run-* recipes
2018-09-25 17:51:41 -07:00
896f9f78c6
Improve generated run-* recipes
...
Or reduce failures and print more failure causes.
2018-09-25 14:31:25 -07:00
9112e6cd28
Merge pull request #1642 from freechipsproject/custom-csr
...
Custom CSR enhancements
2018-09-25 12:40:05 -07:00
eb7c319c53
Add chicken-bit CSR; use it for D$ clock gate
...
The reset value is conservative (don't clock gate).
2018-09-24 23:01:35 -07:00
cd5e116741
Refactor CustomCSRs for extensibility beyond Rocket
2018-09-24 19:26:24 -07:00
7038875bc4
Fix whitespace
2018-09-24 19:09:14 -07:00
83540637ba
Set marchid to 1, which means "Rocket"
2018-09-24 16:59:50 -07:00
58c2b41712
Factor out rocket-specific aspects of CustomCSRs
2018-09-24 16:59:10 -07:00
aedb7ca882
firrtl now does not remove BlackBoxes with no ports by default ( #1630 )
2018-09-24 12:55:50 -07:00
fe116541a6
Change coarse-grained NAPOT PMPs to match spec
...
There was a flaw in the spec and the current proposed fix is cb4515bbd5
2018-09-23 17:20:31 -07:00
17f3d9bdba
Merge pull request #1638 from freechipsproject/dcache-clock-gate
...
D$ improvements
2018-09-22 19:50:03 -07:00
2983a867ce
Optionally clock-gate the PTW
2018-09-22 17:46:45 -07:00
75ee5f01df
Fix another LR/SC starvation case
2018-09-22 17:45:42 -07:00
88f5fe93e3
Separate PTW arbitration request from valid signal
...
This gets rid of a critical path.
2018-09-22 17:17:52 -07:00
8f1e1be817
Refactor D$ clock gating to make it totally local
2018-09-22 17:17:52 -07:00
a67271804b
Make HellaCache implementation overridable
2018-09-22 17:17:52 -07:00
7ebb55cf2c
Support overriding the indexing functions in DCache
2018-09-22 17:17:52 -07:00
06eb72008e
Add some more UInt helpers
2018-09-22 17:17:52 -07:00
981c628195
Automatically clock-gate the D$ when it's idle
2018-09-21 22:58:21 -07:00
Wesley W. Terpstra