Add Simple Custom Instruction Extension
This enables adding custom instructions that operate on the x-registers (i.e., no additional architectural state). This version on supports combinational units (which fit in the pipeline in the same place as the integer ALU), but it can be extended to support 2-stage pipelines, or multi-cycle operations.
This commit is contained in:
Andrew Waterman
parent
ef62d93743
commit
fcfedefc09
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@ -8,6 +8,7 @@ import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.tile.HasCoreParameters
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import freechips.rocketchip.tile.HasCoreParameters
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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import freechips.rocketchip.scie.SCIE
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import Instructions._
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import Instructions._
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import ALU._
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import ALU._
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@ -25,6 +26,7 @@ class IntCtrlSigs extends Bundle {
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val jalr = Bool()
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val jalr = Bool()
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val rxs2 = Bool()
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val rxs2 = Bool()
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val rxs1 = Bool()
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val rxs1 = Bool()
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val scie = Bool()
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val sel_alu2 = Bits(width = A2_X.getWidth)
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val sel_alu2 = Bits(width = A2_X.getWidth)
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val sel_alu1 = Bits(width = A1_X.getWidth)
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val sel_alu1 = Bits(width = A1_X.getWidth)
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val sel_imm = Bits(width = IMM_X.getWidth)
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val sel_imm = Bits(width = IMM_X.getWidth)
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@ -47,19 +49,19 @@ class IntCtrlSigs extends Bundle {
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val dp = Bool()
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val dp = Bool()
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def default: List[BitPat] =
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def default: List[BitPat] =
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// jal renf1 fence.i
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// jal renf1 fence.i
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// val | jalr | renf2 |
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// val | jalr | renf2 |
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// | fp_val| | renx2 | | renf3 |
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// | fp_val| | renx2 | | renf3 |
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// | | rocc| | | renx1 s_alu1 mem_val | | | wfd |
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// | | rocc| | | renx1 s_alu1 mem_val | | | wfd |
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// | | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | mul |
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// | | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | mul |
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// | | | | | | | | | | | | | | | | | | | | | div | fence
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// | | | | | | | | | | | | | | | | | | | | | div | fence
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// | | | | | | | | | | | | | | | | | | | | | | wxd | | amo
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// | | | | | | | | | | | | | | | | | | | | | | wxd | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | | | dp
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// | | | | | | | | scie | | | | | | | | | | | | | | | | | dp
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List(N,X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X)
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List(N,X,X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,X,X,X,X,CSR.X,X,X,X,X)
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def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
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def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
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val decoder = DecodeLogic(inst, default, table)
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val decoder = DecodeLogic(inst, default, table)
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val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
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val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, scie, sel_alu2,
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sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
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sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
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rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp)
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rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp)
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sigs zip decoder map {case(s,d) => s := d}
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sigs zip decoder map {case(s,d) => s := d}
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@ -70,100 +72,100 @@ class IntCtrlSigs extends Bundle {
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class IDecode(implicit val p: Parameters) extends DecodeConstants
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class IDecode(implicit val p: Parameters) extends DecodeConstants
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{
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{
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val table: Array[(BitPat, List[BitPat])] = Array(
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val table: Array[(BitPat, List[BitPat])] = Array(
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BNE-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BNE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BEQ-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BEQ-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BLT-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BLT-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BLTU-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BLTU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BGE-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BGE-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BGEU-> List(Y,N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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BGEU-> List(Y,N,N,Y,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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JAL-> List(Y,N,N,N,Y,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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JAL-> List(Y,N,N,N,Y,N,N,N,N,A2_SIZE,A1_PC, IMM_UJ,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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JALR-> List(Y,N,N,N,N,Y,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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JALR-> List(Y,N,N,N,N,Y,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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AUIPC-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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AUIPC-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LB-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LB-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LH-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LH-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LBU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LBU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LHU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LHU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SB-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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SB-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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SH-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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SH-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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SW-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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SW-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
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LUI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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LUI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ADDI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ADDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTI -> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTI -> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTIU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTIU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ANDI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ANDI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ORI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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XORI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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XORI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ADD-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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ADD-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SUB-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SUB-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLT-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLT-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLTU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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AND-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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AND-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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OR-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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OR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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XOR-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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XOR-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SLL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SRL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SRL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
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SRA-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRA-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
|
|
||||||
FENCE-> List(Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
|
FENCE-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
|
||||||
FENCE_I-> List(Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, Y,M_FLUSH_ALL,MT_X, N,N,N,N,N,N,N,CSR.N,Y,N,N,N),
|
FENCE_I-> List(Y,N,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, Y,M_FLUSH_ALL,MT_X, N,N,N,N,N,N,N,CSR.N,Y,N,N,N),
|
||||||
|
|
||||||
SCALL-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
SCALL-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||||
SBREAK-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
SBREAK-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||||
MRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
MRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||||
WFI-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
WFI-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N),
|
||||||
CSRRW-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
CSRRW-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
||||||
CSRRS-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
CSRRS-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
||||||
CSRRC-> List(Y,N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N),
|
CSRRC-> List(Y,N,N,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N),
|
||||||
CSRRWI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
CSRRWI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
|
||||||
CSRRSI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
CSRRSI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
|
||||||
CSRRCI-> List(Y,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N))
|
CSRRCI-> List(Y,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.C,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class SDecode(implicit val p: Parameters) extends DecodeConstants
|
class SDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, MT_W, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, MT_W, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
SRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
|
SRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class DebugDecode(implicit val p: Parameters) extends DecodeConstants
|
class DebugDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
DRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
|
DRET-> List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class I32Decode(implicit val p: Parameters) extends DecodeConstants
|
class I32Decode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
SLLI_RV32-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SLLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRLI_RV32-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRLI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRAI_RV32-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
SRAI_RV32-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class I64Decode(implicit val p: Parameters) extends DecodeConstants
|
class I64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
LD-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
LD-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
LWU-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
LWU-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SD-> List(Y,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
SD-> List(Y,N,N,N,N,N,Y,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
|
|
||||||
SLLI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SLLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRLI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRLI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRAI-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRAI-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
|
|
||||||
ADDIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
ADDIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SLLIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SLLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRLIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRLIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRAIW-> List(Y,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRAIW-> List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
ADDW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
ADDW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SUBW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SUBW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SLLW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SLLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRLW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
SRLW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
SRAW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
SRAW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class MDecode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
|
class MDecode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
|
||||||
|
|
@ -171,15 +173,15 @@ class MDecode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeC
|
||||||
val M = if (pipelinedMul) Y else N
|
val M = if (pipelinedMul) Y else N
|
||||||
val D = if (pipelinedMul) N else Y
|
val D = if (pipelinedMul) N else Y
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
MUL-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
MUL-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
||||||
MULH-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
MULH-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
||||||
MULHU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
MULHU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
||||||
MULHSU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
MULHSU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
||||||
|
|
||||||
DIV-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
DIV-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
DIVU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
DIVU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
REM-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
REM-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
REMU-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
|
REMU-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class M64Decode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
|
class M64Decode(pipelinedMul: Boolean)(implicit val p: Parameters) extends DecodeConstants
|
||||||
|
|
@ -187,155 +189,161 @@ class M64Decode(pipelinedMul: Boolean)(implicit val p: Parameters) extends Decod
|
||||||
val M = if (pipelinedMul) Y else N
|
val M = if (pipelinedMul) Y else N
|
||||||
val D = if (pipelinedMul) N else Y
|
val D = if (pipelinedMul) N else Y
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
MULW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
MULW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, N,N,N,N,M,D,Y,CSR.N,N,N,N,N),
|
||||||
|
|
||||||
DIVW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
DIVW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
DIVUW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
DIVUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
REMW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
REMW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N),
|
||||||
REMUW-> List(Y,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
|
REMUW-> List(Y,N,N,N,N,N,Y,Y,N,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,N,N,N,N,Y,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class ADecode(implicit val p: Parameters) extends DecodeConstants
|
class ADecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOADD_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOXOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOSWAP_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOAND_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOOR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMIN_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMINU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMAX_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMAXU_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
|
|
||||||
LR_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
LR_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
SC_W-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
|
SC_W-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class A64Decode(implicit val p: Parameters) extends DecodeConstants
|
class A64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOADD_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOSWAP_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOXOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOAND_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOOR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMIN_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMINU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMAX_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
AMOMAXU_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
|
|
||||||
LR_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
LR_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N),
|
||||||
SC_D-> List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
|
SC_D-> List(Y,N,N,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,N,N,N,N,Y,CSR.N,N,N,Y,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class FDecode(implicit val p: Parameters) extends DecodeConstants
|
class FDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FSGNJ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FSGNJX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FSGNJN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FMIN_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FMIN_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FMAX_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FMAX_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FMUL_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FMUL_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
FMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
FMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FNMADD_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
FNMADD_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
FNMSUB_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FCLASS_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FCLASS_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FMV_X_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FMV_X_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FCVT_W_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FCVT_WU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FEQ_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FEQ_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FLT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FLT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FLE_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FLE_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FMV_S_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FCVT_S_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FCVT_S_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FLW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FLW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FSW-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,Y,N,N,N,N,N,CSR.N,N,N,N,N),
|
FSW-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,Y,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
FDIV_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FDIV_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FSQRT_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N))
|
FSQRT_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class DDecode(implicit val p: Parameters) extends DecodeConstants
|
class DDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FCVT_S_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FCVT_D_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FSGNJ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FSGNJX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FSGNJN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FMIN_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMIN_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FMAX_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMAX_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FMUL_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMUL_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FNMADD_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
FNMADD_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
FNMSUB_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FCLASS_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FCLASS_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FCVT_W_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FCVT_WU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FEQ_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FEQ_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FLT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FLT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FLE_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FLE_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FCVT_D_W-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FCVT_D_WU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FLD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FLD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSD-> List(Y,Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y),
|
FSD-> List(Y,Y,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,Y,N,N,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FDIV_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FDIV_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FSQRT_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y))
|
FSQRT_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,N,CSR.N,N,N,N,Y))
|
||||||
}
|
}
|
||||||
|
|
||||||
class F64Decode(implicit val p: Parameters) extends DecodeConstants
|
class F64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FCVT_L_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
FCVT_LU_S-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
FCVT_S_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N),
|
||||||
FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N))
|
FCVT_S_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class D64Decode(implicit val p: Parameters) extends DecodeConstants
|
class D64Decode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
FMV_X_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FMV_X_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FCVT_L_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
FCVT_LU_D-> List(Y,Y,N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,N,Y,CSR.N,N,N,N,Y),
|
||||||
FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FMV_D_X-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
FCVT_D_L-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y),
|
||||||
FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y))
|
FCVT_D_LU-> List(Y,Y,N,N,N,N,N,Y,N,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,N,CSR.N,N,N,N,Y))
|
||||||
|
}
|
||||||
|
|
||||||
|
class SCIEDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
|
{
|
||||||
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
|
SCIE.opcode-> List(Y,N,N,N,N,N,Y,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_X, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
||||||
class RoCCDecode(implicit val p: Parameters) extends DecodeConstants
|
class RoCCDecode(implicit val p: Parameters) extends DecodeConstants
|
||||||
{
|
{
|
||||||
val table: Array[(BitPat, List[BitPat])] = Array(
|
val table: Array[(BitPat, List[BitPat])] = Array(
|
||||||
CUSTOM0-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM0-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM0_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM0_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM0_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM0_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM0_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM1-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM1-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM1_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM1_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM1_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM1_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM1_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM2-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM2-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM2_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM2_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM2_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM2_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM2_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM3-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM3-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM3_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
CUSTOM3_RS1_RS2-> List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,N,CSR.N,N,N,N,N),
|
||||||
CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM3_RD-> List(Y,N,Y,N,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
CUSTOM3_RD_RS1-> List(Y,N,Y,N,N,N,N,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
|
||||||
CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
CUSTOM3_RD_RS1_RS2->List(Y,N,Y,N,N,N,Y,Y,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,Y,CSR.N,N,N,N,N))
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -10,6 +10,7 @@ import freechips.rocketchip.config.Parameters
|
||||||
import freechips.rocketchip.tile._
|
import freechips.rocketchip.tile._
|
||||||
import freechips.rocketchip.util._
|
import freechips.rocketchip.util._
|
||||||
import freechips.rocketchip.util.property._
|
import freechips.rocketchip.util.property._
|
||||||
|
import freechips.rocketchip.scie._
|
||||||
import scala.collection.immutable.ListMap
|
import scala.collection.immutable.ListMap
|
||||||
import scala.collection.mutable.ArrayBuffer
|
import scala.collection.mutable.ArrayBuffer
|
||||||
|
|
||||||
|
|
@ -21,6 +22,7 @@ case class RocketCoreParams(
|
||||||
useAtomics: Boolean = true,
|
useAtomics: Boolean = true,
|
||||||
useAtomicsOnlyForIO: Boolean = false,
|
useAtomicsOnlyForIO: Boolean = false,
|
||||||
useCompressed: Boolean = true,
|
useCompressed: Boolean = true,
|
||||||
|
useSCIE: Boolean = false,
|
||||||
nLocalInterrupts: Int = 0,
|
nLocalInterrupts: Int = 0,
|
||||||
nBreakpoints: Int = 1,
|
nBreakpoints: Int = 1,
|
||||||
nPMPs: Int = 8,
|
nPMPs: Int = 8,
|
||||||
|
|
@ -127,11 +129,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||||
|
|
||||||
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
|
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
|
||||||
val decode_table = {
|
val decode_table = {
|
||||||
|
require(!usingRoCC || !rocketParams.useSCIE)
|
||||||
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
|
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
|
||||||
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
|
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
|
||||||
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
|
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
|
||||||
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
|
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
|
||||||
(usingRoCC.option(new RoCCDecode)) ++:
|
(usingRoCC.option(new RoCCDecode)) ++:
|
||||||
|
(rocketParams.useSCIE.option(new SCIEDecode)) ++:
|
||||||
(if (xLen == 32) new I32Decode else new I64Decode) +:
|
(if (xLen == 32) new I32Decode else new I64Decode) +:
|
||||||
(usingVM.option(new SDecode)) ++:
|
(usingVM.option(new SDecode)) ++:
|
||||||
(usingDebug.option(new DebugDecode)) ++:
|
(usingDebug.option(new DebugDecode)) ++:
|
||||||
|
|
@ -222,6 +226,12 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||||
val id_sfence = id_ctrl.mem && id_ctrl.mem_cmd === M_SFENCE
|
val id_sfence = id_ctrl.mem && id_ctrl.mem_cmd === M_SFENCE
|
||||||
val id_csr_flush = id_sfence || id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
|
val id_csr_flush = id_sfence || id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
|
||||||
|
|
||||||
|
val scie_decoder = rocketParams.useSCIE.option {
|
||||||
|
val d = Module(new SCIEDecoder)
|
||||||
|
assert(!d.io.pipelined && !d.io.multicycle)
|
||||||
|
d.io.insn := id_raw_inst(0)
|
||||||
|
d.io
|
||||||
|
}
|
||||||
val id_illegal_insn = !id_ctrl.legal ||
|
val id_illegal_insn = !id_ctrl.legal ||
|
||||||
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
|
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
|
||||||
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
|
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
|
||||||
|
|
@ -229,6 +239,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||||
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
|
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
|
||||||
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
|
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
|
||||||
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
|
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
|
||||||
|
id_ctrl.scie && scie_decoder.map(!_.unpipelined).getOrElse(false.B) ||
|
||||||
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
|
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
|
||||||
!ibuf.io.inst(0).bits.rvc && ((id_sfence || id_system_insn) && csr.io.decode(0).system_illegal)
|
!ibuf.io.inst(0).bits.rvc && ((id_sfence || id_system_insn) && csr.io.decode(0).system_illegal)
|
||||||
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
|
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
|
||||||
|
|
@ -308,6 +319,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||||
alu.io.in2 := ex_op2.asUInt
|
alu.io.in2 := ex_op2.asUInt
|
||||||
alu.io.in1 := ex_op1.asUInt
|
alu.io.in1 := ex_op1.asUInt
|
||||||
|
|
||||||
|
val scie_unpipelined = rocketParams.useSCIE.option {
|
||||||
|
val u = Module(new SCIEUnpipelined(xLen))
|
||||||
|
u.io.insn := ex_reg_inst
|
||||||
|
u.io.rs1 := ex_rs(0)
|
||||||
|
u.io.rs2 := ex_rs(1)
|
||||||
|
u.io.rd
|
||||||
|
}
|
||||||
|
|
||||||
// multiplier and divider
|
// multiplier and divider
|
||||||
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
|
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
|
||||||
div.io.req.valid := ex_reg_valid && ex_ctrl.div
|
div.io.req.valid := ex_reg_valid && ex_ctrl.div
|
||||||
|
|
@ -438,7 +457,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||||
mem_reg_inst := ex_reg_inst
|
mem_reg_inst := ex_reg_inst
|
||||||
mem_reg_raw_inst := ex_reg_raw_inst
|
mem_reg_raw_inst := ex_reg_raw_inst
|
||||||
mem_reg_pc := ex_reg_pc
|
mem_reg_pc := ex_reg_pc
|
||||||
mem_reg_wdata := alu.io.out
|
mem_reg_wdata := scie_unpipelined.map(u => Mux(ex_ctrl.scie, u, alu.io.out)).getOrElse(alu.io.out)
|
||||||
mem_br_taken := alu.io.cmp_out
|
mem_br_taken := alu.io.cmp_out
|
||||||
|
|
||||||
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
|
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
// See LICENSE.SiFive for license details.
|
||||||
|
|
||||||
|
package freechips.rocketchip.scie
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util.{BitPat, HasBlackBoxInline}
|
||||||
|
import chisel3.experimental.{IntParam, fromIntToIntParam}
|
||||||
|
|
||||||
|
object SCIE {
|
||||||
|
val opcode = BitPat("b?????????????????????????0?01011")
|
||||||
|
val iLen = 32
|
||||||
|
}
|
||||||
|
|
||||||
|
class SCIEDecoderInterface extends Bundle {
|
||||||
|
val insn = Input(UInt(SCIE.iLen.W))
|
||||||
|
val unpipelined = Output(Bool())
|
||||||
|
val pipelined = Output(Bool())
|
||||||
|
val multicycle = Output(Bool())
|
||||||
|
}
|
||||||
|
|
||||||
|
class SCIEDecoder extends BlackBox with HasBlackBoxInline {
|
||||||
|
val io = IO(new SCIEDecoderInterface)
|
||||||
|
|
||||||
|
setInline("SCIEDecoder.v",
|
||||||
|
s"""
|
||||||
|
|module SCIEDecoder (
|
||||||
|
| input [${SCIE.iLen-1}:0] insn,
|
||||||
|
| output unpipelined,
|
||||||
|
| output pipelined,
|
||||||
|
| output multicycle);
|
||||||
|
|
|
||||||
|
| /* This module decodes a SCIE instruction and indicates which functional unit
|
||||||
|
| to send the instruction to (unpipelined, pipelined, or multicycle). The
|
||||||
|
| outputs are don't-cares unless insn lies within the custom-0 or custom-1
|
||||||
|
| major opcodes. If it is within custom-0 or custom-1, then at most one of
|
||||||
|
| the outputs may be high. If none are high, an illegal-instruction trap
|
||||||
|
| occurs. If multiple are high, the behavior is undefined.
|
||||||
|
|
|
||||||
|
| This example implementation permits Funct3 = 0 or 1 within both custom-0
|
||||||
|
| and custom-1 as Unpipelined instructions.
|
||||||
|
| */
|
||||||
|
|
|
||||||
|
| assign unpipelined = (insn[14:12] <= 3'b1);
|
||||||
|
| assign pipelined = 1'b0;
|
||||||
|
| assign multicycle = 1'b0;
|
||||||
|
|
|
||||||
|
|endmodule
|
||||||
|
""".stripMargin)
|
||||||
|
}
|
||||||
|
|
||||||
|
class SCIEUnpipelinedInterface(xLen: Int) extends Bundle {
|
||||||
|
val insn = Input(UInt(SCIE.iLen.W))
|
||||||
|
val rs1 = Input(UInt(xLen.W))
|
||||||
|
val rs2 = Input(UInt(xLen.W))
|
||||||
|
val rd = Output(UInt(xLen.W))
|
||||||
|
}
|
||||||
|
|
||||||
|
class SCIEUnpipelined(xLen: Int) extends BlackBox(Map("XLEN" -> xLen)) with HasBlackBoxInline {
|
||||||
|
val io = IO(new SCIEUnpipelinedInterface(xLen))
|
||||||
|
|
||||||
|
setInline("SCIEUnpipelined.v",
|
||||||
|
s"""
|
||||||
|
|module SCIEUnpipelined #(parameter XLEN = 32) (
|
||||||
|
| input [${SCIE.iLen-1}:0] insn,
|
||||||
|
| input [XLEN-1:0] rs1,
|
||||||
|
| input [XLEN-1:0] rs2,
|
||||||
|
| output [XLEN-1:0] rd);
|
||||||
|
|
|
||||||
|
| /* This example SCIE implementation provides the following instructions:
|
||||||
|
|
|
||||||
|
| Major opcode custom-0:
|
||||||
|
| Funct3 = 0: MIN (rd = rs1 < rs2 ? rs1 : rs2)
|
||||||
|
| Funct3 = 1: MAX (rd = rs1 > rs2 ? rs1 : rs2)
|
||||||
|
|
|
||||||
|
| Major opcode custom-1:
|
||||||
|
| Funct3 = 0: MINI (rd = rs1 < imm[11:0] ? rs1 : imm[11:0])
|
||||||
|
| Funct3 = 1: MAXI (rd = rs1 > imm[11:0] ? rs1 : imm[11:0])
|
||||||
|
| */
|
||||||
|
|
|
||||||
|
| /* Decode the instruction. */
|
||||||
|
| wire use_immediate = insn[5];
|
||||||
|
| wire pick_smaller = !insn[12];
|
||||||
|
|
|
||||||
|
| /* Mux the operands. */
|
||||||
|
| wire [XLEN-1:0] immediate = {{(XLEN-12){insn[31]}}, insn[31:20]};
|
||||||
|
| wire [XLEN-1:0] rhs = use_immediate ? immediate : rs2;
|
||||||
|
| wire [XLEN-1:0] lhs = rs1;
|
||||||
|
|
|
||||||
|
| /* Perform the computation. */
|
||||||
|
| wire lhs_smaller = $$signed(lhs) < $$signed(rhs);
|
||||||
|
| wire [XLEN-1:0] result = lhs_smaller == pick_smaller ? lhs : rhs;
|
||||||
|
|
|
||||||
|
| /* Drive the output. */
|
||||||
|
| assign rd = result;
|
||||||
|
|
|
||||||
|
|endmodule
|
||||||
|
""".stripMargin)
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue