Merge pull request #1820 from freechipsproject/fix-generator
generator: support the no rocket tiles case
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commit
e59b2844bc
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@ -47,41 +47,43 @@ object Generator extends GeneratorApp {
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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override def addTestSuites {
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import DefaultTestSuites._
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val xlen = params(XLen)
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// TODO: for now only generate tests for the first core in the first subsystem
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val tileParams = params(RocketTilesKey).head
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val coreParams = tileParams.core
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val vm = coreParams.useVM
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv32ud))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv64ud))
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params(RocketTilesKey).headOption.map { tileParams =>
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val coreParams = tileParams.core
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val vm = coreParams.useVM
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val env = if (vm) List("p","v") else List("p")
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coreParams.fpu foreach { case cfg =>
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if (xlen == 32) {
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TestGeneration.addSuites(env.map(rv32uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv32ud))
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} else {
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64uf))
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if (cfg.fLen >= 64)
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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}
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if (coreParams.useAtomics) {
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if (tileParams.dcache.flatMap(_.scratch).isEmpty)
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
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else
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
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}
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if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
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else ((if (vm) rv32i else rv32pi), rv32u)
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if (coreParams.useAtomics) {
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if (tileParams.dcache.flatMap(_.scratch).isEmpty)
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
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else
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TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
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}
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if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
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else ((if (vm) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
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}
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}
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val longName = names.configProject + "." + names.configs
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