Don't rely on SeqMem output after read-enable is low

src/main/scala/uncore/axi4/SRAM.scala

@@ -59,9 +59,13 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
       r_id := in.ar.bits.id
     }
 
+    val ren = in.ar.fire()
+    def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
+    val rdata = holdUnless(mem.read(r_addr, ren), RegNext(ren))
+
     in.r.bits.id   := r_id
     in.r.bits.resp := AXI4Parameters.RESP_OKAY
-    in.r.bits.data := Cat(mem.read(r_addr, in.ar.fire()).reverse)
+    in.r.bits.data := Cat(rdata.reverse)
     in.r.bits.last := Bool(true)
   }
 }

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -71,7 +71,9 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
     when (in.a.fire() && !read) {
       mem.write(memAddress, wdata, in.a.bits.mask.toBools)
     }
-    rdata := mem.read(memAddress, in.a.fire() && read)
+    val ren = in.a.fire() && read
+    def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
+    rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren))
 
     // Tie off unused channels
     in.b.valid := Bool(false)