Object model (#1684)
* Added Object Model case classes * Added objectionModelInstance function to SimpleDevice * Added object model JSON elaboration artifact. * Added companion object and OMISA factory
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@ -3,6 +3,7 @@
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package freechips.rocketchip.diplomacy
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import Chisel.log2Ceil
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import freechips.rocketchip.diplomaticobjectmodel.model._
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import scala.collection.immutable.{ListMap,SortedMap}
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import scala.collection.mutable.HashMap
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@ -68,6 +69,10 @@ abstract class Device
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{
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def describe(resources: ResourceBindings): Description
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/* This can be overriden to make one device relative to another */
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def objectModelInstance() : Option[OMComponent] = None
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def parent: Option[Device] = None
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/** make sure all derived devices have an unique label */
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@ -359,6 +364,8 @@ trait BindingScope
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/** Collect resource addresses from tree. */
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def collectResourceAddresses = collect(2, Nil, 0, bindingTree)
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def objectModelInstance: Option[OMComponent] = None
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}
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object BindingScope
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@ -0,0 +1,26 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomaticobjectmodel
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import java.io.{File, FileWriter}
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import java.lang.management.OperatingSystemMXBean
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import org.json4s.jackson.JsonMethods.pretty
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import org.json4s.jackson.Serialization
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import org.json4s.{Extraction, NoTypeHints}
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object DiplomaticObjectModelUtils {
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def toJson(json: Any): String = {
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implicit val formats = Serialization.formats(NoTypeHints)
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pretty(Extraction.decompose(json))
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}
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def writeJsonFile(filename: String, json: Map[String, Any]) : Unit = {
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val writer = new FileWriter(new File(filename))
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writer.write(toJson(json))
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writer.close()
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}
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}
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@ -0,0 +1,42 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomaticobjectmodel.model
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sealed trait PrivilegedArchitectureExtension
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case object MachineLevelISA extends PrivilegedArchitectureExtension
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case object SupervisorLevelISA extends PrivilegedArchitectureExtension
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object PrivilegedArchitectureExtensions {
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val specifications = Map[PrivilegedArchitectureExtension, String](
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MachineLevelISA -> "Machine-Level ISA",
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SupervisorLevelISA -> "Supervisor-Level ISA"
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)
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def specVersion(extension: PrivilegedArchitectureExtension, version: String): OMSpecification = OMSpecification(specifications(extension), version)
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}
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object BaseExtensions {
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val specifications = Map[OMBaseInstructionSet, String](
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RV32E -> "RV32E Base Integer Instruction Set",
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RV32I -> "RV32I Base Integer Instruction Set",
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RV64I -> "RV64I Base Integer Instruction Set"
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)
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def specVersion(extension: OMBaseInstructionSet, version: String): OMSpecification = OMSpecification(specifications(extension), version)
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}
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object ISAExtensions {
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val specifications = Map[OMExtensionType, String](
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M -> "M Standard Extension for Integer Multiplication and Division",
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A -> "A Standard Extension for Atomic Instruction",
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F -> "F Standard Extension for Single-Precision Floating-Point",
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D -> "D Standard Extension for Double-Precision Floating-Point",
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C -> "C Standard Extension for Compressed Instruction",
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U -> "TODO This is not really correct. The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture",
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S -> "Supervisor-Level ISA"
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)
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def specVersion(extension: OMExtensionType, version: String): OMSpecification = OMSpecification(specifications(extension), version)
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}
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@ -0,0 +1,12 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomaticobjectmodel.model
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trait OMBaseType
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trait OMEnum extends OMBaseType
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trait OMCompoundType extends OMBaseType
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trait OMComponent extends OMCompoundType
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@ -0,0 +1,37 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomaticobjectmodel.model
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trait OMExtensionType extends OMEnum
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case object M extends OMExtensionType
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case object A extends OMExtensionType
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case object F extends OMExtensionType
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case object D extends OMExtensionType
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case object C extends OMExtensionType
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case object U extends OMExtensionType
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case object S extends OMExtensionType
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trait OMAddressTranslationMode extends OMEnum
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case object Sv32 extends OMAddressTranslationMode
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case object Sv39 extends OMAddressTranslationMode
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case object Sv48 extends OMAddressTranslationMode
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trait OMBaseInstructionSet extends OMEnum
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case object RV32E extends OMBaseInstructionSet
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case object RV32I extends OMBaseInstructionSet
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case object RV64I extends OMBaseInstructionSet
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case object RV128I extends OMBaseInstructionSet
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case class OMISA(
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xLen: Int,
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baseSpecification: OMSpecification,
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base: OMBaseInstructionSet,
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m: Option[OMSpecification],
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a: Option[OMSpecification],
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f: Option[OMSpecification],
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d: Option[OMSpecification],
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c: Option[OMSpecification],
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u: Option[OMSpecification],
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s: Option[OMSpecification],
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addressTranslationModes: Seq[OMAddressTranslationMode]
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) extends OMCompoundType
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@ -0,0 +1,8 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomaticobjectmodel.model
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case class OMSpecification(
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name: String,
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version: String
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)
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@ -5,6 +5,7 @@ package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.DiplomaticObjectModelUtils
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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@ -19,6 +20,7 @@ case object BuildSystemBus extends Field[Parameters => SystemBus](p => new Syste
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/** BareSubsystem is the root class for creating a subsystem */
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abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with BindingScope {
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lazy val objectModelJson = DiplomaticObjectModelUtils.toJson(objectModelInstance)
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lazy val dts = DTS(bindingTree)
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lazy val dtb = DTB(dts)
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lazy val json = JSON(bindingTree)
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@ -26,6 +28,7 @@ abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with Bin
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abstract class BareSubsystemModuleImp[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) {
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val outer = _outer
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ElaborationArtefacts.add("objectModel.json", outer.objectModelJson)
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ElaborationArtefacts.add("graphml", outer.graphML)
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ElaborationArtefacts.add("dts", outer.dts)
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ElaborationArtefacts.add("json", outer.json)
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