tilelink: enhance trivial arbiters to reduce to nothing
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@ -42,6 +42,8 @@ object TLArbiter
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def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*) {
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def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*) {
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if (sources.isEmpty) {
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if (sources.isEmpty) {
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sink.valid := Bool(false)
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sink.valid := Bool(false)
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} else if (sources.size == 1) {
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sink <> sources.head._2
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} else {
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} else {
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val pairs = sources.toList
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val pairs = sources.toList
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val beatsIn = pairs.map(_._1)
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val beatsIn = pairs.map(_._1)
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@ -77,15 +79,10 @@ object TLArbiter
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val muxState = Mux(idle, winner, state)
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val muxState = Mux(idle, winner, state)
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state := muxState
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state := muxState
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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val allowed = Mux(idle, readys, state)
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(sourcesIn zip allowed) foreach { case (s, r) =>
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(sourcesIn zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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s.ready := sink.ready && r
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}
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} else {
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sourcesIn(0).ready := sink.ready
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}
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}
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sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
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sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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}
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}
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@ -242,7 +242,7 @@ object TLXbar
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val filtered = Wire(Vec(select.size, input))
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val filtered = Wire(Vec(select.size, input))
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for (i <- 0 until select.size) {
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for (i <- 0 until select.size) {
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filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
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filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
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filtered(i).valid := input.valid && select(i)
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filtered(i).valid := input.valid && (select(i) || Bool(select.size == 1))
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}
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}
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input.ready := Mux1H(select, filtered.map(_.ready))
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input.ready := Mux1H(select, filtered.map(_.ready))
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filtered
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filtered
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