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Merge pull request #1330 from freechipsproject/async-reset-reg-cleanup 

vsrc: AsyncResetReg adjustments
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Henry Cook 2018-04-11 00:09:07 -07:00 committed by GitHub
parent 8f3009feb1 d0e6a6aaaa
commit d4afacd37b
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1 changed files with 16 additions and 14 deletions
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30
src/main/resources/vsrc/AsyncResetReg.v
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@ -39,43 +39,45 @@
module AsyncResetReg (
input d,
output reg q,
output q,
input en,
input clk,
input rst);
reg q_reg;
initial begin
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
`endif
`endif // RANDOMIZE
if (rst) begin
`ifdef verilator
q = 1'b0;
`endif
q_reg = 1'b0;
end
`ifdef RANDOMIZE
`ifndef verilator
`endif
`ifdef RANDOMIZE_REG_INIT
else begin
`ifndef verilator
#0.002 begin end
q = _RAND[0];
`endif // verilator
q_reg = _RAND[0];
end
`endif
`endif // `ifdef RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
q_reg <= 1'b0;
end else if (en) begin
q <= d;
q_reg <= d;
end
end
assign q = rst ? 1'b0 : q_reg;
endmodule // AsyncResetReg