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Merge pull request #1849 from freechipsproject/fpu-clock-gate 

Move FPU load pipeline register into ungated clock domain
This commit is contained in:
Andrew Waterman 2019-02-20 17:04:54 -08:00 committed by GitHub
parent a05728c4fa bb5cae70d8
commit d29c1ac9b6
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 6 deletions
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12
src/main/scala/tile/FPU.scala
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@ -680,6 +680,12 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt())) val ex_ra = List.fill(3)(Reg(UInt()))
// load response
val load_wb = Reg(next=io.dmem_resp_val)
val load_wb_double = RegEnable(io.dmem_resp_type(0), io.dmem_resp_val)
val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
@chiselName class FPUImpl { // entering gated-clock domain @chiselName class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid val req_valid = ex_reg_valid || io.cp_req.valid
@ -705,12 +711,6 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val mem_ctrl = RegEnable(ex_ctrl, req_valid) val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// load response
val load_wb = Reg(next=io.dmem_resp_val)
val load_wb_double = RegEnable(io.dmem_resp_type(0), io.dmem_resp_val)
val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
// regfile // regfile
val regfile = Mem(32, Bits(width = fLen+1)) val regfile = Mem(32, Bits(width = fLen+1))
when (load_wb) { when (load_wb) {