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Merge pull request #1854 from freechipsproject/mimpid-parameter 

Make the mimpid CSR value a parameter
This commit is contained in:
Andrew Waterman 2019-02-23 18:46:47 -08:00 committed by GitHub
parent d29c1ac9b6 d1403b0a2e
commit cf67a65d42
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 6 additions and 6 deletions
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8
src/main/scala/rocket/DCache.scala
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@ -163,6 +163,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: Nil = Enum(UInt(), 8)
val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
val flushed = Reg(init=Bool(true))
val flushing = Reg(init=Bool(false))
val cached_grant_wait = Reg(init=Bool(false))
val release_ack_wait = Reg(init=Bool(false))
val can_acquire_before_release = !release_ack_wait && release_queue_empty
@ -330,7 +331,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
dontTouch(s2_victim_dirty)
val s2_update_meta = s2_hit_state =/= s2_new_hit_state
val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready
val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed || s2_cmd_flush_line)
val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed && !flushing || s2_cmd_flush_line)
io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_flush && !s2_valid_hit
when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
@ -788,7 +789,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val resetting = RegInit(false.B)
if (!usingDataScratchpad)
when (RegNext(reset)) { resetting := true }
val flushing = Reg(init=Bool(false))
val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))
val flushCounterNext = flushCounter +& 1
val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays
@ -806,8 +806,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// Only flush D$ on FENCE.I if some cached executable regions are untracked.
if (supports_flush) {
when (s2_valid_masked && s2_cmd_flush_all) {
when (!flushed) {
flushing := !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR
when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) {
flushing := true
}
}

4
src/main/scala/rocket/RocketCore.scala
View File

@ -38,6 +38,7 @@ case class RocketCoreParams(
branchPredictionModeCSR: Boolean = false,
clockGate: Boolean = false,
mvendorid: Int = 0, // 0 means non-commercial implementation
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams())
) extends CoreParams {
@ -83,8 +84,7 @@ class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocket
def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
// mimpid encodes a release version in the form of a BCD-encoded datestamp.
// Past releases: <none>
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(0x20181004))
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
}