Use Vec instead of Seq for better naming
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@ -159,8 +159,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack
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// I/O MSHRs
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val uncachedInFlight = Seq.fill(maxUncachedInFlight) { RegInit(Bool(false)) }
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val uncachedReqs = Seq.fill(maxUncachedInFlight) { Reg(new HellaCacheReq) }
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val uncachedInFlight = RegInit(Vec.fill(maxUncachedInFlight)(false.B))
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val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq))
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// hit initiation path
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val s0_read = isRead(io.cpu.req.bits.cmd)
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