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Bump chisel3 

Summary of changes:
* Basic BundleLiteral support
* Add lit*Option methods for extracting literals
* Improved numbering of _T_*
* Undeprecate log2Up and log2Down
* BoringUtils for synthesizable cross module references
* Seq[Data] illegal in Bundle, override with ignoreSeq
* MixedVec
* Module Inlining and Flattening Support
* Verilog memory loading
* Access module ports via DataMirror.modulePorts
* Support for .B on [Big]Ints
* Stack Trace Trimming
* toBool[s] -> asBool[s]
* Improved UInt.-% emission
This commit is contained in:
Jack Koenig 2019-01-07 17:30:24 -08:00
parent e3a9ee30f2
commit b4c7188413
1 changed files with 1 additions and 1 deletions
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chisel3

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Subproject commit 3d8064a9f2fd49bffb402b91131087c19ca7d6fc Subproject commit 9a0ce2272c9d5d0a8bdc90e84269749ce054664d