Fix CLINT MSIP register addressing
This finishes the work started in 1d95fcc882
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@ -21,7 +21,7 @@ object CLINTConsts
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def timecmpBytes = 8
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def size = 0x10000
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def timeWidth = 64
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def ipiWidth = 1
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def ipiWidth = 32
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def ints = 2
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}
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@ -83,8 +83,8 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
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*/
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node.regmap(
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0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) =>
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RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
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0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
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RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
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timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
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RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
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timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),
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