From afd93df40e3a9b4196a1c75487ec9e0db6c747f3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 3 Oct 2018 17:25:51 -0700 Subject: [PATCH] Fix CLINT MSIP register addressing This finishes the work started in 1d95fcc882b1761ad2d0a2572dc8938aca805ef1 --- src/main/scala/devices/tilelink/CLINT.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala index 00b416ab..71860325 100644 --- a/src/main/scala/devices/tilelink/CLINT.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -21,7 +21,7 @@ object CLINTConsts def timecmpBytes = 8 def size = 0x10000 def timeWidth = 64 - def ipiWidth = 1 + def ipiWidth = 32 def ints = 2 } @@ -83,8 +83,8 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends */ node.regmap( - 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => - RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}), + 0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) => + RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }), timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))}, timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),