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Fix CLINT MSIP register addressing 

This finishes the work started in 1d95fcc882
This commit is contained in:
Andrew Waterman 2018-10-03 17:25:51 -07:00
parent 696955394a
commit afd93df40e
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/devices/tilelink/CLINT.scala
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@ -21,7 +21,7 @@ object CLINTConsts
def timecmpBytes = 8
def size = 0x10000
def timeWidth = 64
def ipiWidth = 1
def ipiWidth = 32
def ints = 2
}
@ -83,8 +83,8 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
*/
node.regmap(
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) =>
RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),