Minor D$ QoR improvement
s2_xcpt doesn't need to drive so many things.
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@ -239,11 +239,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s1_all_data_ways = Vec(data.io.resp :+ dummyEncodeData(tl_out.d.bits.data))
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val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).mask)
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val s2_valid_pre_xcpt = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false))
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val s2_valid = s2_valid_pre_xcpt && !io.cpu.s2_xcpt.asUInt.orR
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val s2_valid = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false))
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val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR
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val s2_probe = Reg(next=s1_probe, init=Bool(false))
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val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready
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val s2_valid_masked = s2_valid && Reg(next = !s1_nack)
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val s2_valid_masked = s2_valid_no_xcpt && Reg(next = !s1_nack)
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val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill
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val s2_req = Reg(io.cpu.req.bits)
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val s2_uncached = Reg(Bool())
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@ -309,7 +309,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
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dontTouch(s2_victim_dirty)
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val s2_update_meta = s2_hit_state =/= s2_new_hit_state
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io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached_pending && tl_out_a.ready)
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io.cpu.s2_nack := s2_valid_no_xcpt && !s2_valid_hit && !(s2_valid_uncached_pending && tl_out_a.ready)
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when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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// tag updates on ECC errors
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@ -828,7 +828,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.keep_clock_enabled ||
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metaArb.io.out.valid || // subsumes resetting || flushing
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s1_probe || s2_probe ||
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s1_valid || s2_valid_pre_xcpt ||
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s1_valid || s2_valid ||
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pstore1_held || pstore2_valid ||
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release_state =/= s_ready ||
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release_ack_wait || !release_queue_empty ||
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