From c569908857c4bf7aa18cb820aa40c9de13c489f8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 15 Feb 2019 15:50:04 -0800 Subject: [PATCH] Increase the number of situations in which frontend can be clock gated The fetch queue needs to fill up, which currently is only possible with certain code sequences. This PR makes the fetch queue flow control exact rather than conservative, removing the software constraint. --- src/main/scala/rocket/Frontend.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index e53397b7..0f266437 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -96,11 +96,16 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBEntries))) - val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3) - val s1_valid = RegNext(s0_valid) + val s1_valid = Reg(Bool()) + val s2_valid = RegInit(false.B) + val s0_fq_has_space = + !fq.io.mask(fq.io.mask.getWidth-3) || + (!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) || + (!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid)) + val s0_valid = io.cpu.req.valid || s0_fq_has_space + s1_valid := s0_valid val s1_pc = Reg(UInt(width=vaddrBitsExtended)) val s1_speculative = Reg(Bool()) - val s2_valid = RegInit(false.B) val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector)) val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B val s2_btb_resp_bits = Reg(new BTBResp)