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subsystem: move inter-bus coupling to child classes of BaseSubsystem

This commit is contained in:
Henry Cook 2018-10-26 00:54:39 -07:00
parent f65bf8215b
commit 89ff3dc548
3 changed files with 30 additions and 23 deletions
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10
src/main/scala/groundtest/GroundTestSubsystem.scala
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@ -35,6 +35,16 @@ class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
// No PLIC in ground test; so just sink the interrupts to nowhere
IntSinkNode(IntSinkPortSimple()) := ibus.toPLIC
sbus.crossToBus(cbus, NoCrossing)
cbus.crossToBus(pbus, SynchronousCrossing())
sbus.crossFromBus(fbus, SynchronousCrossing())
private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
private val (in, out, halt) = coherenceManager(this)
if (nBanks != 0) {
sbus.coupleTo("coherence_manager") { in :*= _ }
mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
}
override lazy val module = new GroundTestSubsystemModuleImp(this)
}

24
src/main/scala/subsystem/BaseSubsystem.scala
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@ -46,29 +46,7 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
val mbus = LazyModule(new MemoryBus(p(MemoryBusKey)))
val cbus = LazyModule(new PeripheryBus(p(ControlBusKey)))
// The sbus masters the cbus; here we convert TL-UH -> TL-UL
sbus.crossToBus(cbus, NoCrossing)
// The cbus masters the pbus; which might be clocked slower
cbus.crossToBus(pbus, SynchronousCrossing())
// The fbus masters the sbus; both are TL-UH or TL-C
FlipRendering { implicit p =>
sbus.crossFromBus(fbus, SynchronousCrossing())
}
// The sbus masters the mbus; here we convert TL-C -> TL-UH
private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
// TODO: the below call to coherenceManager should be wrapped in a LazyScope here,
// but plumbing halt is too annoying for now.
private val (in, out, halt) = coherenceManager(this)
def memBusCanCauseHalt: () => Option[Bool] = halt
if (nBanks != 0) {
sbus.coupleTo("coherence_manager") { in :*= _ }
mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
}
// Collect information for use in DTS
lazy val topManagers = ManagerUnification(sbus.busView.manager.managers)
ResourceBinding {
val managers = topManagers

19
src/main/scala/system/ExampleRocketSystem.scala
View File

@ -18,6 +18,25 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
with CanHaveSlaveAXI4Port
with HasPeripheryBootROM {
override lazy val module = new ExampleRocketSystemModuleImp(this)
// The sbus masters the cbus; here we convert TL-UH -> TL-UL
sbus.crossToBus(cbus, NoCrossing)
// The cbus masters the pbus; which might be clocked slower
cbus.crossToBus(pbus, SynchronousCrossing())
// The fbus masters the sbus; both are TL-UH or TL-C
FlipRendering { implicit p =>
sbus.crossFromBus(fbus, SynchronousCrossing())
}
// The sbus masters the mbus; here we convert TL-C -> TL-UH
private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
private val (in, out, halt) = coherenceManager(this)
if (nBanks != 0) {
sbus.coupleTo("coherence_manager") { in :*= _ }
mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
}
}
class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)