Cleanup jtag dtm (#342)
* debug: Clean up Debug TransportModule synchronizer With async reset async queues, I feel its safe/cleaner to remove the one-off "AsyncMailbox verilog black-box and use the common primitive. I also added some comments about correct usage of this block. Probably the 'TRST' signal should be renamed to make it less confusing, as it requires some processing of the real JTAG 'TRST' signal.
This commit is contained in:
mwachs5
GitHub
parent
8641639873
commit
77a0f76289
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@ -222,7 +222,7 @@ JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
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stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-TestHarness-$* \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_DIR)/bin/openocd \
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--s $(OPENOCD_DIR)/share/openocd/scripts" \
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--freedom-e300-sim \
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@ -231,7 +231,7 @@ stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebu
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stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-TestHarness-$* \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
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--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
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--freedom-u500-sim \
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@ -13,29 +13,34 @@ case object IncludeJtagDTM extends Field[Boolean]
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* This implements JTAG interface described
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* in the RISC-V Debug Specification
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*
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* This Module is currently a
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* wrapper around a number of black-boxed
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* modules. The black-boxing is due to the fact that
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* This Module is currently a
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* wrapper around a JTAG implementation
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* of the Debug Transport Module.
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* This is black-boxed because
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* Chisel doesn't currently support:
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* - Negative Edge Clocking
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* - Asynchronous Resets
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* (The tristate requirements of JTAG are exported from the
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* Chisel domain with the DRV_TDO signal).
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*
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* The AsyncDebugBus parameter here is overloaded.
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* The DebugTransportModule JTAG definately needs a synchronizer,
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* the parameter just currently selects whether the Chisel-generated
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* crossing is used or the black-boxed crossing is used.
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* Although Top is also capable of generating the
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* Chisel sychnronizers, it is done here for consistency
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* of keeping the synchronizers in one place when
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* instantiating the DTM.
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*
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* The 'TRST' input is used to asynchronously
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* reset the Debug Transport Module and the
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* DTM side of the synchronizer.
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* This design requires that TRST be
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* synchronized to TCK (for de-assert) outside
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* of this module. Your top level code should ensure
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* that TRST is asserted before the rocket-chip core
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* comes out of reset.
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* Note that TRST is an optional
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* part of the JTAG protocol, but it is not
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* optional for interfacing with this logic.
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*
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*/
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class JtagDTMWithSync(implicit val p: Parameters) extends Module {
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class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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extends Module {
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// IO <-> [Chisel Sync?] <-> [DebugBusIO<->UInt] <-> [Black Box Sync?] <-> DTM Black Box
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// io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box
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val io = new Bundle {
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@ -56,14 +61,7 @@ class JtagDTMWithSync(implicit val p: Parameters) extends Module {
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val io_debug_bus = Wire (new DebugBusIO)
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// Optionally instantiate the Chisel synchronizers.
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// These go on this side of the DebugBusIO->UInt translation
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// because the Chisel synchronizers understand these data structures.
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if (p(AsyncDebugBus)){
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io.debug <> AsyncDebugBusFrom(io.jtag.TCK, io.jtag.TRST, io_debug_bus)
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} else {
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io.debug <> io_debug_bus
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}
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io.debug <> AsyncDebugBusFrom(io.jtag.TCK, io.jtag.TRST, io_debug_bus, depth, sync)
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// Translate from straight 'bits' interface of the blackboxes
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// into the Resp/Req data structures.
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@ -74,32 +72,6 @@ class JtagDTMWithSync(implicit val p: Parameters) extends Module {
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dtm_resp.valid := io_debug_bus.resp.valid
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dtm_resp.bits := io_debug_bus.resp.bits.asUInt
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io_debug_bus.resp.ready := dtm_resp.ready
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// Optionally instantiate the black-box synchronizers
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// instead of the chisel ones.
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// These go on this side of the DebugBusIO->UInt translation
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// because they do not understand the DebugBusIO data structures.
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if (p(AsyncDebugBus)) {
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dtm_req <> jtag_dtm.io.dtm_req
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jtag_dtm.io.dtm_resp <> dtm_resp
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} else {
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val req_sync = Module (new AsyncMailbox())
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val resp_sync = Module (new AsyncMailbox())
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req_sync.io.enq := jtag_dtm.io.dtm_req
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req_sync.io.enq_clock := io.jtag.TCK
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req_sync.io.enq_reset := io.jtag.TRST
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req_sync.io.deq_clock := clock
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req_sync.io.deq_reset := reset
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dtm_req := req_sync.io.deq
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jtag_dtm.io.dtm_resp := resp_sync.io.deq
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resp_sync.io.deq_clock := io.jtag.TCK
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resp_sync.io.deq_reset := io.jtag.TRST
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resp_sync.io.enq_clock := clock
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resp_sync.io.enq_reset := reset
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resp_sync.io.enq := dtm_resp
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}
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}
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class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {
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@ -985,7 +985,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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object AsyncDebugBusCrossing {
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// takes from_source from the 'from' clock domain to the 'to' clock domain
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def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, to_clock: Clock, to_reset: Bool, depth: Int = 3, sync: Int = 2) = {
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def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, to_clock: Clock, to_reset: Bool, depth: Int = 1, sync: Int = 3) = {
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val to_sink = Wire(new DebugBusIO()(from_source.p))
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to_sink.req <> AsyncDecoupledCrossing(from_clock, from_reset, from_source.req, to_clock, to_reset, depth, sync)
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from_source.resp <> AsyncDecoupledCrossing(to_clock, to_reset, to_sink.resp, from_clock, from_reset, depth, sync)
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@ -6,7 +6,6 @@
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bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
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$(base_dir)/vsrc/jtag_vpi.v \
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$(base_dir)/vsrc/AsyncMailbox.v \
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$(base_dir)/vsrc/AsyncResetReg.v \
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$(base_dir)/vsrc/AsyncSetReg.v \
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@ -1,154 +0,0 @@
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module AsyncMailbox (
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// Write Interface
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enq_clock
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, enq_reset
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, enq_ready
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, enq_valid
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, enq_bits
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// Read Interface
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, deq_clock
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, deq_reset
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, deq_ready
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, deq_valid
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, deq_bits
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);
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//--------------------------------------------------------
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// Parameter Declarations
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parameter WIDTH = 64;
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//--------------------------------------------------------
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// I/O Declarations
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// Write Interface
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input enq_clock;
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wire w_clock = enq_clock;
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input enq_reset;
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wire w_reset = enq_reset;
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output enq_ready;
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wire w_ready;
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assign enq_ready = w_ready;
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input enq_valid;
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wire w_valid = enq_valid;
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input [WIDTH - 1 : 0 ] enq_bits;
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wire [WIDTH - 1 : 0 ] w_bits = enq_bits;
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// Read Interface
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input deq_clock;
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wire r_clock = deq_clock;
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input deq_reset;
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wire r_reset = deq_reset;
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output deq_valid;
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wire r_valid;
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assign deq_valid = r_valid;
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input deq_ready;
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wire r_ready = deq_ready;
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output [WIDTH - 1 : 0] deq_bits;
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wire [WIDTH - 1 : 0] r_bits;
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assign deq_bits = r_bits;
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//--------------------------------------------------------
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// FIFO Memory Declaration
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reg [WIDTH - 1 :0] mailboxReg;
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//--------------------------------------------------------
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// Reg and Wire Declarations
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wire w_full;
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wire w_fire;
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wire r_empty;
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wire r_fire;
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// Read & Write Address Pointers
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reg w_wrAddrReg;
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wire w_wrAddrNxt;
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reg r_rdAddrReg;
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wire r_rdAddrNxt;
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reg wrAddrReg_sync;
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reg rdAddrReg_sync;
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reg r_wrAddrReg;
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reg w_rdAddrReg;
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//--------------------------------------------------------
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// Reg and Wire Declarations
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assign w_full = ~(w_wrAddrReg == r_rdAddrReg);
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assign w_wrAddrNxt = ~w_wrAddrReg ;
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assign r_rdAddrNxt = ~r_rdAddrReg;
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assign r_empty = (r_wrAddrReg == r_rdAddrReg);
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assign w_ready = ~w_full;
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assign w_fire = w_ready & w_valid;
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// Read Logic
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assign r_valid = ~r_empty;
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assign r_fire = r_ready & r_valid;
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assign r_bits = mailboxReg;
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always @(posedge w_clock) begin
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if (w_fire) begin
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mailboxReg <= w_bits;
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end
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end
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//--------------------------------------------------------
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// Sequential logic
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//
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always @(posedge w_clock or posedge w_reset) begin
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if (w_reset ) begin
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w_wrAddrReg <= 1'b0;
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rdAddrReg_sync <= 1'b0;
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w_rdAddrReg <= 1'b0;
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end else begin
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if (w_fire) begin
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w_wrAddrReg <= w_wrAddrNxt;
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end
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rdAddrReg_sync <= r_rdAddrReg;
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w_rdAddrReg <= rdAddrReg_sync;
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end
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end
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always @(posedge r_clock or posedge r_reset) begin
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if (r_reset) begin
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r_rdAddrReg <= 1'b0;
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wrAddrReg_sync <= 1'b0;
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r_wrAddrReg <= 1'b0;
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end else begin
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if (r_fire) begin
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r_rdAddrReg <= r_rdAddrNxt;
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end
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wrAddrReg_sync <= w_wrAddrReg;
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r_wrAddrReg <= wrAddrReg_sync;
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end
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end // always @ (posedge r_clock)
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endmodule // AsyncMailbox
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