Pass ClockCrossingType into DCache; use it instead of knownRatio
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@ -40,7 +40,7 @@ abstract class GroundTestTile(params: GroundTestTileParams)
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val haltNode: IntOutwardNode = IntIdentityNode()
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val wfiNode: IntOutwardNode = IntIdentityNode()
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val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
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val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0, crossing)) }
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override lazy val module = new GroundTestTileModuleImp(this)
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}
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@ -5,7 +5,7 @@ package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tile.LookupByHartId
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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@ -79,7 +79,7 @@ class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p)
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val data = UInt(width = cacheParams.tagCode.width(new L1Metadata().getWidth))
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}
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class DCache(hartid: Int, val bufferUncachedRequests: Option[Int] = None)(implicit p: Parameters) extends HellaCache(hartid)(p) {
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class DCache(hartid: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(hartid)(p) {
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override lazy val module = new DCacheModule(this)
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}
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@ -121,10 +121,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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metaArb.io.out.ready := clock_en_reg
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val tl_out_a = Wire(tl_out.a)
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tl_out.a <> outer.bufferUncachedRequests
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.map(_ min maxUncachedInFlight-1)
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.map(Queue(tl_out_a, _, flow = true))
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.getOrElse(tl_out_a)
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tl_out.a <> {
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val a_queue_depth = outer.crossing match {
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case RationalCrossing(_) => 2 min maxUncachedInFlight-1 // TODO make this depend on the actual ratio?
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case SynchronousCrossing(_) => 0
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}
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Queue(tl_out_a, a_queue_depth, flow = true)
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}
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val (tl_out_c, release_queue_empty) =
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if (cacheParams.acquireBeforeRelease) {
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@ -851,8 +854,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid))
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io.cpu.perf.blocked := {
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// stop reporting blocked just before unblocking to avoid overly conservative stalling
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val cycles = outer.bufferUncachedRequests.map(n => if (n > 1) 1 else 2).getOrElse(2)
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cached_grant_wait && d_address_inc < ((cacheBlockBytes - cycles * beatBytes) max 0)
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val beatsBeforeEnd = outer.crossing match {
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case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2
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case SynchronousCrossing(_) => 2
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}
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cached_grant_wait && d_address_inc < ((cacheBlockBytes - beatsBeforeEnd * beatBytes) max 0)
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}
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// report errors
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@ -224,7 +224,7 @@ trait HasHellaCache { this: BaseTile =>
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var nDCachePorts = 0
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lazy val dcache: HellaCache = LazyModule(
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if(tileParams.dcache.get.nMSHRs == 0) {
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new DCache(hartId, p(RocketCrossingKey).head.knownRatio)
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new DCache(hartId, crossing)
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} else { new NonBlockingDCache(hartId) })
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tlMasterXbar.node := dcache.node
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