Revert "Core monitor bundle (#1746)" (#1750)

This reverts commit c69607cfd5.

src/main/scala/rocket/RocketCore.scala

@@ -89,23 +89,6 @@ class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocket
   override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
 }
 
-// this bundle is used to expose some internal core signals
-// to verification monitors which sample instruction commits
-class CoreMonitorBundle(val xLen: Int) extends Bundle {
-  val hartid = UInt(width = xLen)
-  val timer = UInt(width = 32)
-  val valid = Bool()
-  val pc = UInt(width = xLen)
-  val wrdst = UInt(width = 5)
-  val wrdata = UInt(width = xLen)
-  val wren = Bool()
-  val rd0src = UInt(width = 5)
-  val rd0val = UInt(width = xLen)
-  val rd1src = UInt(width = 5)
-  val rd1val = UInt(width = xLen)
-  val inst = UInt(width = 32)
-}
-
 @chiselName
 class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     with HasRocketCoreParameters
@@ -819,10 +802,24 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
   csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
 
-  val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen))
+  class CoreMonitorBundle extends Bundle {
+    val hartid = UInt(width = hartIdLen)
+    val time = UInt(width = 32)
+    val valid = Bool()
+    val pc = UInt(width = vaddrBitsExtended)
+    val wrdst = UInt(width = 5)
+    val wrdata = UInt(width = xLen)
+    val wren = Bool()
+    val rd0src = UInt(width = 5)
+    val rd0val = UInt(width = xLen)
+    val rd1src = UInt(width = 5)
+    val rd1val = UInt(width = xLen)
+    val inst = UInt(width = 32)
+  }
+  val coreMonitorBundle = Wire(new CoreMonitorBundle)
 
   coreMonitorBundle.hartid := io.hartid
-  coreMonitorBundle.timer := csr.io.time(31,0)
+  coreMonitorBundle.time := csr.io.time(31,0)
   coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
   coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0)
   coreMonitorBundle.wrdst := Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0))
@@ -834,6 +831,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   coreMonitorBundle.rd1val := Reg(next=Reg(next=ex_rs(1)))
   coreMonitorBundle.inst := csr.io.trace(0).insn
 
+  p(BundleMonitorKey).foreach { _ ("rocket_core_monitor", coreMonitorBundle) }
+
   if (enableCommitLog) {
     val t = csr.io.trace(0)
     val rd = wb_waddr
@@ -862,7 +861,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   }
   else {
     printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
-         coreMonitorBundle.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
+         coreMonitorBundle.hartid, coreMonitorBundle.time, coreMonitorBundle.valid,
          coreMonitorBundle.pc,
          coreMonitorBundle.wrdst, coreMonitorBundle.wrdata, coreMonitorBundle.wren,
          coreMonitorBundle.rd0src, coreMonitorBundle.rd0val,

src/main/scala/util/BundleMonitorKey.scala

@@ -0,0 +1,12 @@
+// See LICENSE.Berkeley for license details.
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.util
+
+import freechips.rocketchip.config._
+import Chisel._
+
+// This key allows to pass a bundle monitor object through parameters
+// It does not define acutal implementation
+
+case object BundleMonitorKey extends Field[Option[(String, Bundle) => Unit]] (None)