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hqjenny-rocket-chip
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Merge pull request #1784 from freechipsproject/seip-clock-gate 

Respect SEIP during WFI clock gate
This commit is contained in:
Andrew Waterman 2019-01-17 10:02:08 -08:00 committed by GitHub
parent 508dd91184 d79cd12252
commit 68380eb9c3
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2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/CSR.scala
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@ -329,7 +329,7 @@ class CSRFile(
mip.msip := io.interrupts.msip
mip.meip := io.interrupts.meip
// seip is the OR of reg_mip.seip and the actual line from the PLIC
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || RegNext(_) }
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val high_interrupts = io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)

2
src/main/scala/rocket/DCache.scala
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@ -777,7 +777,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
ccover(s2_valid_masked && s2_req.cmd === M_FLUSH_ALL && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush")
ccover(s2_valid_masked && s2_req.cmd === M_FLUSH_ALL && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush")
s1_flush_valid := metaArb.io.in(5).fire() && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait
metaArb.io.in(5).valid := flushing
metaArb.io.in(5).valid := flushing && !flushed
metaArb.io.in(5).bits.write := false
metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0)
metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits)